riscv
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OpenFPGA
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2 Commits

Author SHA1 Message Date
ganeshgore f6b3c5854a Bugfix : 
+ OpenFPGA template variables update
+ Default path for the verilog netlist
 2020-04-11 16:45:22 -06:00
ganeshgore 7f98ecc8a6 OpenFPGA shell run test script template 2020-04-06 00:32:43 -06:00