tangxifan
|
e31dc1f2f2
|
openfpga shell now support continued line charactor '\'
|
2020-04-07 21:27:51 -06:00 |
|
tangxifan
|
33315f0521
|
now openfpga shell allow empty space at beginning and end of each line in script mode
|
2020-04-07 20:46:45 -06:00 |
|
tangxifan
|
0b1c8ac139
|
bug fixed in identifying the physical interconnect for pb_graph nodes
|
2020-04-07 19:46:42 -06:00 |
|
tangxifan
|
50bb04d496
|
add scan-chain test case. Debugging on the way
|
2020-04-07 16:50:41 -06:00 |
|
tangxifan
|
6d6295ef93
|
Add test cases about using standard cell mux2
|
2020-04-07 11:12:47 -06:00 |
|
tangxifan
|
d39d7a68ce
|
add test cases for using tree-like multiplexer
|
2020-04-07 10:46:49 -06:00 |
|
tangxifan
|
6eb125ec2a
|
Now cross-column/row is optional to direct annotation in OpenFPGA architecture XML
|
2020-04-06 14:09:52 -06:00 |
|
tangxifan
|
ca45efd13d
|
add testing script for the spy io
|
2020-04-05 15:24:40 -06:00 |
|
tangxifan
|
32c74ad811
|
added FPGA architecture with I/Os on the left and right sides
|
2020-04-01 15:46:38 -06:00 |
|
tangxifan
|
07e1979498
|
add architecture examples on wide memory blocks (width=2). tileable routing is working
|
2020-03-28 15:41:26 -06:00 |
|
tangxifan
|
e601a648cc
|
relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics
|
2020-03-27 19:07:34 -06:00 |
|
tangxifan
|
7c9c2451f2
|
debugging multiple io_types; bug fixed to support I/Os in more flexible location of FPGA fabric
|
2020-03-27 16:03:42 -06:00 |
|
tangxifan
|
b09b051249
|
add all the test cases considering tileable, carry chain, direct connection and memory blocks
|
2020-03-27 13:58:35 -06:00 |
|
tangxifan
|
b6bdf78d95
|
bug fixed for heterogeneous block instances in top module
|
2020-03-24 17:39:26 -06:00 |
|
tangxifan
|
3958ac2494
|
fix bugs in flow manager on default compress routing problems
|
2020-03-22 15:26:15 -06:00 |
|
tangxifan
|
7b9384f3b2
|
add write_gsb command to shell interface
|
2020-03-21 19:40:26 -06:00 |
|
tangxifan
|
9a518e8bb6
|
bug fixed for tileable rr_graph builder for more 4x4 fabrics
|
2020-03-21 18:07:00 -06:00 |
|
tangxifan
|
708fda9606
|
fixed a bug in using tileable routing when directlist is enabled
|
2020-03-20 16:38:58 -06:00 |
|
tangxifan
|
9837be618d
|
start debugging tile direct with micro architecture
|
2020-03-20 14:52:52 -06:00 |
|
tangxifan
|
a0b150f12e
|
adding micro architecture using adder chain
|
2020-03-20 14:18:59 -06:00 |
|
tangxifan
|
29450f3472
|
debugging multi-source lb router
|
2020-03-12 20:42:41 -06:00 |
|
tangxifan
|
2a260a05aa
|
add a microbenchmark `and_latch` to test LUTs in wired mode
|
2020-03-11 10:40:59 -06:00 |
|
tangxifan
|
aff73bdd74
|
deployed edge sorting and make it as an option to link_arch command
|
2020-03-08 15:59:53 -06:00 |
|
tangxifan
|
3241d8bd37
|
put analysis sdc writer online. Minor bug in redudant '/' to be fixed
|
2020-03-02 19:54:18 -07:00 |
|
tangxifan
|
a17c14c363
|
clean-up command addition and add fabric bitstream building to sample script
|
2020-03-02 10:39:19 -07:00 |
|
tangxifan
|
7b18f7cd09
|
now the auto select number of clocks in simulation is online
|
2020-02-29 13:29:16 -07:00 |
|
tangxifan
|
9fd184e3ab
|
rm out-of-date script
|
2020-02-28 15:42:18 -07:00 |
|
tangxifan
|
05ebd77d7d
|
start debugging with micro benchmarks. Spot problem in local routing
|
2020-02-28 15:41:32 -07:00 |
|
tangxifan
|
80bb2baae5
|
start verification and bug fixing
|
2020-02-28 14:29:01 -07:00 |
|
tangxifan
|
092e10afda
|
bring pnr sdc generator online and fixed minor bugs in bitstream writing
|
2020-02-28 11:14:50 -07:00 |
|
tangxifan
|
65c81e14b2
|
add simulation ini file writer
|
2020-02-27 18:01:47 -07:00 |
|
tangxifan
|
078f72320f
|
debugging Verilog testbench generator. Bug spotted in using renamed atom_block and clock ports
|
2020-02-27 13:24:26 -07:00 |
|
tangxifan
|
25e0583636
|
add io location map data structure and start porting verilog testbench generator
|
2020-02-26 17:10:57 -07:00 |
|
tangxifan
|
a26d31b87f
|
make write bitstream online
|
2020-02-26 11:09:23 -07:00 |
|
tangxifan
|
51439ba3b4
|
add bitstream writer to be integrated
|
2020-02-23 20:40:18 -07:00 |
|
tangxifan
|
b035b4c87f
|
debugged with Lbrouter. Next step is to output routing traces to physical pb data structure
|
2020-02-21 12:16:50 -07:00 |
|
tangxifan
|
3e07d7d5e0
|
finish net addition to LbRouter. Found a bug in pb pin fix-up. Need to consider clustered I/O block z offset
|
2020-02-20 20:26:20 -07:00 |
|
tangxifan
|
fdb27c5a6b
|
move lb_rr_graph construction to repack command
|
2020-02-20 13:24:34 -07:00 |
|
tangxifan
|
409b3f6896
|
add lb_rr_graph builder for the refactored version
|
2020-02-17 21:11:56 -07:00 |
|
tangxifan
|
c6c3ef71f3
|
adapt all the Verilog submodule writers and bring it onlien
|
2020-02-16 13:35:18 -07:00 |
|
tangxifan
|
8b0df8632c
|
bring fpga verilog create directory online
|
2020-02-15 20:38:45 -07:00 |
|
tangxifan
|
13fadd0f91
|
move compact routing hierarchy to build_fabric command
|
2020-02-12 15:49:47 -07:00 |
|
tangxifan
|
175bef014a
|
add compact_routing hierarchy command
|
2020-02-11 17:40:37 -07:00 |
|
tangxifan
|
ed9e038845
|
add functionality of LUT truth table fix-up
|
2020-02-06 17:14:29 -07:00 |
|
tangxifan
|
dad204674b
|
done an initial version of clustering net fix-up based on routing results. Debugging on the way
|
2020-02-05 21:50:52 -07:00 |
|
tangxifan
|
5006a4395d
|
bring RRGraph object and writer online
|
2020-01-31 16:39:40 -07:00 |
|
tangxifan
|
02d6256e95
|
pass simple test on pb_type annotation for frac_lut5 architecture
|
2020-01-30 21:39:44 -07:00 |
|
tangxifan
|
568ed120c2
|
change report naming fix-up to be XML format
|
2020-01-29 21:53:56 -07:00 |
|
tangxifan
|
2dc4c26257
|
add naming fix-up
|
2020-01-29 17:49:33 -07:00 |
|
tangxifan
|
8c86c0af04
|
add check netlist naming conflict command and functions
|
2020-01-29 16:23:41 -07:00 |