tangxifan
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177de90822
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bug fix in example scripts
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2020-07-26 22:10:04 -06:00 |
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tangxifan
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f687774452
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bug fix in template scripts
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2020-07-26 21:46:03 -06:00 |
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tangxifan
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41a76126b9
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add fabric bitstream writer to CI
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2020-07-26 21:44:42 -06:00 |
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tangxifan
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c87f6b75b9
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add test case for FPGA-SPICE
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2020-07-24 19:12:35 -06:00 |
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tangxifan
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adea6fcec4
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add bitstream generation only test case to CI
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2020-07-02 16:31:22 -06:00 |
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tangxifan
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d526f08782
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deploy bitstream reader in openfpga shell
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2020-06-20 18:48:19 -06:00 |
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tangxifan
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3d56cd3060
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fine tuning on the script for MCNC benchmarks
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2020-06-15 20:09:46 -06:00 |
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tangxifan
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2d35848cfa
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add external key test cases
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2020-06-12 13:11:21 -06:00 |
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tangxifan
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65b387a589
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develop test cases for fabric keys
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2020-06-12 11:32:52 -06:00 |
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tangxifan
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cf9c3b0f44
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add write fabric to test cases
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2020-06-12 10:50:23 -06:00 |
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tangxifan
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068d9943e7
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update all the templates and regression test cases with simulation settings
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2020-06-11 19:31:16 -06:00 |
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tangxifan
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1842bf51e1
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deploy read_openfpga_simulation_setting in CI on a single test case
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2020-06-11 19:31:16 -06:00 |
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tangxifan
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96b58dfdbb
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use new simulation setting command in openfpga shell
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2020-06-11 19:31:15 -06:00 |
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tangxifan
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288294c23a
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add fast configuration test case for memory bank configuration protocol
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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8b3e79766c
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add fast configuration option to fpga_verilog to speed up full testbench simulation
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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1e73fd6def
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create configuration frame example script
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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bba476fef4
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add explicit port mapping support to Verilog testbench generator
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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910be3cadb
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massively deploy disable_timing for configure ports in CI
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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13f591cacf
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add new command to disable timing for configure ports of programmable modules
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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fc2b09514e
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add configuration chain write to regression tests
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2020-06-11 19:31:06 -06:00 |
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tangxifan
|
1943929353
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add write_fabric_hierarchy to regression tests
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2020-06-11 19:31:04 -06:00 |
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tangxifan
|
98fbcb5410
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add time unit test for SDC generation to CI
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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42cede37fa
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add testcases on generate fabric/testbench only
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2020-06-11 19:31:01 -06:00 |
ganeshgore
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49edeb119c
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BugFix : Relative path for refrence benchmark fixed
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2020-06-11 19:28:13 -06:00 |
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tangxifan
|
417d534121
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fine tune mcnc example script to run Modelsim simulations easily
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2020-04-23 16:15:45 -06:00 |
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tangxifan
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df85175765
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fine tuning on mcnc example script so that we can run run_modelsim.py --runsim
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2020-04-22 21:44:52 -06:00 |
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tangxifan
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f9fcc6b471
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tweak mcnc scripts by stop VRP to remove buffers. Now passed mcnc big20 in Verilog/Bitstream generation
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2020-04-22 18:24:09 -06:00 |
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tangxifan
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7ba3e27371
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add duplicated_grid_pin test case to Travis CI
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2020-04-12 20:10:51 -06:00 |
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tangxifan
|
e78643f108
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add flatten routing test case to Travis CI
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2020-04-12 20:06:40 -06:00 |
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tangxifan
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59ea0a6ad5
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add implicit verilog test case to Travis CI
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2020-04-12 20:00:20 -06:00 |
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ganeshgore
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f6b3c5854a
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Bugfix :
+ OpenFPGA template variables update
+ Default path for the verilog netlist
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2020-04-11 16:45:22 -06:00 |
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ganeshgore
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7f98ecc8a6
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OpenFPGA shell run test script template
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2020-04-06 00:32:43 -06:00 |