tangxifan
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0eeb8e5317
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clean up example architecture XML by removing redundant syntax
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2020-04-07 11:24:42 -06:00 |
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tangxifan
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6d6295ef93
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Add test cases about using standard cell mux2
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2020-04-07 11:12:47 -06:00 |
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tangxifan
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d39d7a68ce
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add test cases for using tree-like multiplexer
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2020-04-07 10:46:49 -06:00 |
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tangxifan
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92a3a444f9
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update VPR7 to support global I/O ports
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2020-04-06 20:44:00 -06:00 |
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Xifan Tang
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7a4137fdcf
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doc update for packable XML syntax in VPR
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2020-04-06 18:37:05 -06:00 |
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tangxifan
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13cd48c119
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add support on packable/unpackable modes in VPR architecture
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2020-04-06 16:07:49 -06:00 |
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tangxifan
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7e89c2c65f
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2020-04-06 14:10:38 -06:00 |
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tangxifan
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6eb125ec2a
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Now cross-column/row is optional to direct annotation in OpenFPGA architecture XML
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2020-04-06 14:09:52 -06:00 |
ganeshgore
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87c25a6084
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Added GCC paths to source
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2020-04-06 00:35:28 -06:00 |
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ganeshgore
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e1db4df744
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Created task for FPGA shell run
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2020-04-06 00:35:07 -06:00 |
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ganeshgore
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ea4122a8a4
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Updated openfpga_flow and task file to support sheel run
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2020-04-06 00:34:36 -06:00 |
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ganeshgore
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7f98ecc8a6
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OpenFPGA shell run test script template
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2020-04-06 00:32:43 -06:00 |
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ganeshgore
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eb3b02277a
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Added XML and benchmarks for testing
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2020-04-06 00:32:06 -06:00 |
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ganeshgore
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77f7e13ba7
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2020-04-05 20:59:10 -06:00 |
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Xifan Tang
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1a3a748dd2
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update documentation with the support on spypads and global I/O ports
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2020-04-05 20:12:28 -06:00 |
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tangxifan
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3369d724e9
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bug fixing in Verilog top-level testbench generation
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2020-04-05 17:50:11 -06:00 |
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tangxifan
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decc1dc4b2
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debugged global gp input/output port support
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2020-04-05 17:39:30 -06:00 |
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tangxifan
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bcb86801fa
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bug fixed in gpio naming for module manager ports
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2020-04-05 17:26:44 -06:00 |
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tangxifan
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5f4e7dc5d4
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support gpinput and gpoutput ports in module manager and circuit library
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2020-04-05 16:52:21 -06:00 |
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tangxifan
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bc47b3ca94
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update verilog module writer to the global spy ports
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2020-04-05 16:04:13 -06:00 |
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tangxifan
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8b583b7917
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debugging spy port builder in module manager
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2020-04-05 16:01:25 -06:00 |
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tangxifan
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ca45efd13d
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add testing script for the spy io
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2020-04-05 15:24:40 -06:00 |
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tangxifan
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3b63ad6657
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add test openfpga arch XML with spy pad
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2020-04-05 15:23:07 -06:00 |
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tangxifan
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836f722f20
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start supporting global output ports in module manager
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2020-04-05 15:19:46 -06:00 |
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ganeshgore
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d1d3446568
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backedup partial upgrade for fpga_flow script
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2020-04-05 11:36:24 -06:00 |
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tangxifan
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32c74ad811
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added FPGA architecture with I/Os on the left and right sides
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2020-04-01 15:46:38 -06:00 |
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Xifan Tang
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6ce0fe4ef2
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doc update for FPGA-bitstream to better motivate the different types of bitstream
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2020-04-01 12:57:28 -06:00 |
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Xifan Tang
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fd8248d9dd
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update documentation: the addon syntax on VPR and configuration protocols
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2020-04-01 12:35:52 -06:00 |
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tangxifan
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63306ce3a0
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add comments to explain the memory organization in the top-level module
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2020-04-01 11:05:30 -06:00 |
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tangxifan
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5d12f499f0
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hotfix on undriven pins on the connection blocks
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2020-03-29 16:26:23 -06:00 |
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tangxifan
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07e1979498
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add architecture examples on wide memory blocks (width=2). tileable routing is working
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2020-03-28 15:41:26 -06:00 |
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tangxifan
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ff9cc50527
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relax I/O circuit model checking to fit AIB interface. Adapt testbench generation for multiple types of I/O pads
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2020-03-27 20:09:50 -06:00 |
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tangxifan
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e601a648cc
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relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics
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2020-03-27 19:07:34 -06:00 |
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tangxifan
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34a1b61ecb
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add an example FPGA architecture with AIB interface at the right side of I/Os
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2020-03-27 18:45:27 -06:00 |
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tangxifan
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4bf0a63ae6
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bug fixed for multiple io types defined in FPGA architectures
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2020-03-27 16:32:15 -06:00 |
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tangxifan
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7c9c2451f2
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debugging multiple io_types; bug fixed to support I/Os in more flexible location of FPGA fabric
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2020-03-27 16:03:42 -06:00 |
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tangxifan
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b09b051249
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add all the test cases considering tileable, carry chain, direct connection and memory blocks
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2020-03-27 13:58:35 -06:00 |
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tangxifan
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78964ce71c
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update documentation on the through channel
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2020-03-27 11:34:39 -06:00 |
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tangxifan
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e47a0a4422
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add through channel architecture example
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2020-03-27 11:32:44 -06:00 |
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tangxifan
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5ce078fe60
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minor fix on rr_graph.clear()
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2020-03-27 11:26:14 -06:00 |
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tangxifan
|
91a618466d
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bug fixing for rr_graph.clear() function
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2020-03-27 10:52:48 -06:00 |
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tangxifan
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3b3c39454b
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update print_route() in VPR to show correct track_id when tileable routing is used
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2020-03-25 17:55:28 -06:00 |
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Xifan Tang
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b4221e94bb
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add documentation on the tileable routing and thru channel support
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2020-03-25 16:52:42 -06:00 |
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Xifan Tang
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cb6afea07c
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update documentation on a new option in FPGA-SDC to constrain zero-delay paths
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2020-03-25 16:00:25 -06:00 |
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tangxifan
|
329b0a9cf1
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add options to enable SDC constraints on zero-delay paths
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2020-03-25 15:55:30 -06:00 |
|
Xifan Tang
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3a74fb7a04
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update documentation for the new options
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2020-03-25 15:23:21 -06:00 |
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tangxifan
|
4a0128f240
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minor fix on the SDC format
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2020-03-25 14:46:31 -06:00 |
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tangxifan
|
62b6de8437
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update the SDC of VPR7+OpenFPGA to be even with VPR8+OpenFPGA
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2020-03-25 14:44:42 -06:00 |
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tangxifan
|
c2e5d6b8e2
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add options to dsiable SDC for non-clock global ports
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2020-03-25 14:38:13 -06:00 |
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tangxifan
|
787dc8ce83
|
added ASCII OpenFPGA logo in shell interface
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2020-03-25 11:16:04 -06:00 |