tangxifan
|
ad432e4d95
|
[Engine] Bug fix in finding the start index of BL/WL for each column/row;
|
2021-09-22 10:20:40 -07:00 |
|
tangxifan
|
b0a471bdc9
|
[Engine] Bug fix in outputting fabric key with coordinates
|
2021-09-21 15:55:11 -07:00 |
|
tangxifan
|
7688c0570f
|
[Engine] Support coordinate definition in fabric key file format; Now QL memory bank can accept fabric key
|
2021-09-21 15:08:08 -07:00 |
|
tangxifan
|
c84c0d4a3f
|
[FPGA-Verilog] Upgrade fpga-verilog to support decoders with WLR
|
2021-09-20 17:07:26 -07:00 |
|
tangxifan
|
36a4da863c
|
[Engine] Support WLR port in OpenFPGA architecture file and fabric generator
|
2021-09-20 16:05:36 -07:00 |
|
tangxifan
|
2e45a6143b
|
[Engine] Fix a critical bug which causes flatten memory tests failed
|
2021-09-15 15:11:58 -07:00 |
|
tangxifan
|
f2aa31ddb1
|
[FPGA-Bitstream] Fix the bug which causes bitstream wrong for QL memory bank
|
2021-09-15 13:45:30 -07:00 |
|
tangxifan
|
061952b7fa
|
[Engine] Bug fix in computing local WLs for GRID/CB/SB
|
2021-09-15 11:51:00 -07:00 |
|
tangxifan
|
26b1e48723
|
[Engine] Merge BL/WLs in the Grid/CB/SB modules
|
2021-09-15 11:27:55 -07:00 |
|
tangxifan
|
4af6413c97
|
[Engine] Fixed a critical bug on WL arrangement; Previously we always consider squart of a local tile. Now we apply global optimization where the number of WLs are determined by the max. number of BLs per column
|
2021-09-10 17:03:44 -07:00 |
|
tangxifan
|
ba1e277dc9
|
[Engine] Fix a few bugs in the BL/WL arrangement and now bitstream generator is working fine
|
2021-09-10 15:05:46 -07:00 |
|
tangxifan
|
35c7b09888
|
[Engine] Bug fix for mistakes in calculating number of BLs/WLs for QL memory bank
|
2021-09-09 15:23:29 -07:00 |
|
tangxifan
|
b787c4e100
|
[Engine] Register QL memory bank as a legal protocol
|
2021-09-09 15:06:51 -07:00 |
|
tangxifan
|
1aac3197eb
|
[FPGA-Verilog] Upgrade testbench generator to support QL memory bank
|
2021-09-05 21:38:00 -07:00 |
|
tangxifan
|
6f09f5f7ad
|
[FPGA-Bitstream] Upgrade bitstream generator to support QL memory bank
|
2021-09-05 21:25:58 -07:00 |
|
tangxifan
|
1085e468e2
|
[Engine] Move most utilized functions for memory bank configuration protocol to a separated source file
|
2021-09-05 20:45:56 -07:00 |
|
tangxifan
|
475ce2c6d9
|
[Engine] Upgrade fabric generator in support QL memory bank connections
|
2021-09-05 17:49:01 -07:00 |
|
tangxifan
|
ed80d6b3f4
|
[Engine] Place QL memory bank source codes in a separated source file so that integration to OpenFPGA open-source version is easier
|
2021-09-05 13:23:38 -07:00 |
|
tangxifan
|
cf2e479d18
|
[Engine] Refactor the TopModuleNumConfigBits data structure
|
2021-09-05 12:01:38 -07:00 |
|
tangxifan
|
f75456e304
|
[Engine] Update BL/WL estimation function for QL memory bank protocol
|
2021-09-05 11:53:33 -07:00 |
|
tangxifan
|
5759f5f35b
|
[Engine] Start developing QL memory bank: upgrade infrastructures of fabric builder
|
2021-09-03 17:55:23 -07:00 |
|
tangxifan
|
e9d29e27e5
|
[Tool] Bug fix
|
2021-07-02 15:32:30 -06:00 |
|
tangxifan
|
6e6c3e9fa4
|
[Tool] Patch the critical bug in the use of signal polarity in pin constraints
|
2021-07-02 15:26:21 -06:00 |
|
tangxifan
|
9074bffa68
|
[Tool] Support customized default value in pin constraint file
|
2021-07-01 23:43:19 -06:00 |
|
tangxifan
|
d0e4f8521f
|
[Tool] Bug fix on the reset stimuli
|
2021-07-01 19:58:54 -06:00 |
|
tangxifan
|
b5df1f9aeb
|
[Tool] Bug fix for redundant endif in netlists
|
2021-06-29 17:02:16 -06:00 |
|
tangxifan
|
b83eef47b4
|
[Tool] Bug fix for testbench generation without self checking codes
|
2021-06-29 16:27:29 -06:00 |
|
tangxifan
|
6a260cadbf
|
[Tool] Remove option ``--no_self_checking`` option but use the existing option ``--reference_benchmark_path`` to achieve the same purpose
|
2021-06-29 15:42:23 -06:00 |
|
tangxifan
|
7ac7de789e
|
[Tool] Add a new option ``--no_self_checking`` so that users can output a simple testbench without self checking codes
|
2021-06-29 15:26:40 -06:00 |
|
tangxifan
|
77dddaeb39
|
[Tool] Remove the preprocessing flags ``FORMAL_SIMULATION`` and ``FORMAL_VERIFICAITON`` because now ``write_testbench`` command can be called many times to generate different versions
|
2021-06-29 14:26:33 -06:00 |
|
tangxifan
|
a3208b332b
|
[Tool] Use 'force' in preconfigured testbenches to avoid instrusive code modification on flip-flop HDL
|
2021-06-29 11:50:53 -06:00 |
|
tangxifan
|
dfe1db996a
|
[Tool] Remove the hardcoded factor when computing simulation timing; There should be no hidden parameters impacting simulation time
|
2021-06-29 09:56:04 -06:00 |
|
tangxifan
|
87446a14c3
|
[Tool] Bug fix for the option ``--embed_bitstream none``
|
2021-06-27 19:45:06 -06:00 |
|
tangxifan
|
991062e9bf
|
[Tool] Bug fix
|
2021-06-25 15:22:42 -06:00 |
|
tangxifan
|
90163fab6c
|
[Tool] Replace option '--support_icarus_simulator' with a new one '--preload_bitstream <string>'
|
2021-06-25 15:06:07 -06:00 |
|
tangxifan
|
2bb514c51a
|
[Tool] Support time unit in writing simulation information file
|
2021-06-25 10:33:29 -06:00 |
|
tangxifan
|
bcc16d732c
|
[Tool] Add new option 'testbench_type' so that simulation task can write different information for different testbenches
|
2021-06-25 10:10:16 -06:00 |
|
tangxifan
|
67dec810eb
|
[Tool] Remove icarus simulator flag; Reduce the file size of preconfigured fabric wrapper by only output the necessary force/deposit HDL codes
|
2021-06-24 17:27:32 -06:00 |
|
tangxifan
|
549657e1fb
|
[Tool] Remove out-of-date flag: INITIAL_SIMULATION from code base
|
2021-06-24 17:13:36 -06:00 |
|
tangxifan
|
5364d8104f
|
[Tool] Add signal_init option to preconfigured fabric wrapper writer
|
2021-06-24 17:07:41 -06:00 |
|
tangxifan
|
21d1519658
|
[Tool] Remove signal initialization flag; Now the HDL codes will not be outputted unless specified in the option
|
2021-06-24 16:56:28 -06:00 |
|
tangxifan
|
ce3c80f499
|
Merge branch 'master' into dev
|
2021-06-23 09:15:03 -06:00 |
|
tangxifan
|
cbbf601edc
|
[Tool] Fix a compiler warning due to uninitialized data structure
|
2021-06-18 16:20:13 -06:00 |
|
tangxifan
|
fed975c52a
|
[Tool] Add postfix removal support in write_io_mapping command
|
2021-06-18 16:13:50 -06:00 |
|
tangxifan
|
d9d57aad42
|
[Tool] Added default net type options to verilog testbench generator command
|
2021-06-14 11:37:49 -06:00 |
|
tangxifan
|
7ade48343c
|
[Tool] Deprecate command 'write_verilog_testbench'
|
2021-06-09 17:06:01 -06:00 |
|
tangxifan
|
2299ce3157
|
[Tool] Preconfigured testbench writer now supports icarus simulator
|
2021-06-09 13:49:25 -06:00 |
|
tangxifan
|
3bc8e760db
|
[Tool] Add '--fabric_netlist' option to 'write_preconfigured_testbench' command
|
2021-06-09 11:14:45 -06:00 |
|
tangxifan
|
89fb672631
|
[Tool] Fine-tune the options of 'write_simulation_task_info' to be straightforward to use
|
2021-06-09 10:49:00 -06:00 |
|
tangxifan
|
97396eda2b
|
[Tool] Add a new command 'write_simulation_task_info'
|
2021-06-08 22:10:02 -06:00 |
|
tangxifan
|
d2275b971d
|
[Tool] Add a new command 'write_preconfigured_testbench'
|
2021-06-08 21:53:51 -06:00 |
|
tangxifan
|
85679c0fe2
|
[Tool] Bug fix in the top testbench switch due to fast configuration
|
2021-06-08 21:32:26 -06:00 |
|
tangxifan
|
8db19c7af9
|
[Tool] Add a new command 'write_preconfigured_fabric_wrapper'
|
2021-06-08 21:28:16 -06:00 |
|
tangxifan
|
5075c68418
|
[Tool] Remove duplicated codes on fast configuration
|
2021-06-08 20:58:04 -06:00 |
|
tangxifan
|
4aef9d5c96
|
[Tool] Remove redundant codes
|
2021-06-07 21:54:01 -06:00 |
|
tangxifan
|
366dcff75d
|
[Tool] Now 'write_full_testbench' supports flatten(vanilla) configuration protocol
|
2021-06-07 21:49:31 -06:00 |
|
tangxifan
|
9808b61b36
|
[Tool] Bug fix on the unfit vector size of bit index register in Verilog testbench in some cases
|
2021-06-07 20:06:39 -06:00 |
|
tangxifan
|
ba75c18378
|
[Tool] Now 'write_full_testbench' supports memory bank configuration protocol
|
2021-06-07 17:40:07 -06:00 |
|
tangxifan
|
1a5902ca74
|
[Tool] Bug fix in finding pruned bitstream for frame-based protocol when fast configuration is enabled
|
2021-06-07 14:32:56 -06:00 |
|
tangxifan
|
af298de121
|
[Tool] Patch bugs in the full testbench writing using external bitstream file for frame-based configuration protocol
|
2021-06-07 13:53:32 -06:00 |
|
tangxifan
|
d644b8f22d
|
[Tool] Support external bitstream file when generating full testbench for frame-based decoder
|
2021-06-07 11:55:11 -06:00 |
|
tangxifan
|
618b04568f
|
[Tool] Remove unnecessary new line in bitstream file
|
2021-06-04 20:07:42 -06:00 |
|
tangxifan
|
cf7addb1a6
|
[Tool] Add heads to bitstream plain text file
|
2021-06-04 19:48:48 -06:00 |
|
tangxifan
|
70fb3a85dc
|
[Tool] Patch fast configuration in bitstream writing
|
2021-06-04 17:23:10 -06:00 |
|
tangxifan
|
d98be9f87b
|
[Tool] Remove icarus requirement on vcd writing in Verilog testbenches; Since vcd writing commands are standard Verilog
|
2021-06-04 16:45:00 -06:00 |
|
tangxifan
|
6e69c2d70a
|
[Tool] Patch fast configuration in full Verilog testbench generator
|
2021-06-04 16:34:55 -06:00 |
|
tangxifan
|
061f832429
|
[Tool] Enable fast configuration when writing fabric bitstream
|
2021-06-04 16:23:40 -06:00 |
|
tangxifan
|
81048d3698
|
[Tool] Add option '--fast_configuration' to 'write_full_testbench' command
|
2021-06-04 11:26:39 -06:00 |
|
tangxifan
|
98308133c1
|
[Tool] Add configuration skip capability to top testbench which loads external bitstream file
|
2021-06-04 11:24:05 -06:00 |
|
tangxifan
|
adb18d28b8
|
[Tool] Remove unused arguments
|
2021-06-04 10:37:28 -06:00 |
|
tangxifan
|
67485269d3
|
Merge branch 'master' into testbench_external_bitstream
|
2021-06-03 15:46:25 -06:00 |
|
tangxifan
|
ae6a46cd60
|
[Tool] Add a new command write_full_testbench which outputs self-testable full testbench which loads external bitstream file; Currently only support configuration chain without fast configuration technique
|
2021-06-03 15:41:11 -06:00 |
|
tangxifan
|
1fd399736d
|
[Tool] Patch FPGA-SDC to consider time unit in global port timing constraints
|
2021-05-27 10:26:20 -06:00 |
|
tangxifan
|
c4ecc9ee7c
|
[Tool] Patch data type of report bitstream distribution command-line option
|
2021-05-07 11:44:01 -06:00 |
|
tangxifan
|
db9bb9124e
|
[Tool] Add report bitstream distribution command to openfpga shell
|
2021-05-07 11:41:25 -06:00 |
|
tangxifan
|
8728fd9561
|
[Tool] Typo fix to resolve clang errors
|
2021-04-27 15:06:07 -06:00 |
|
tangxifan
|
c5d36757c6
|
[Tool] Fix typo in io mapping writing
|
2021-04-27 14:39:57 -06:00 |
|
tangxifan
|
43c1e052ef
|
[Tool] Add a writer to output I/O mapping information to XML files
|
2021-04-27 14:30:16 -06:00 |
|
tangxifan
|
148da80869
|
[Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes
|
2021-04-24 14:53:29 -06:00 |
|
tangxifan
|
0709e5bb81
|
[Tool] Fixed a bug in the routing trace finder for direct connections inside repacker
|
2021-04-24 13:27:44 -06:00 |
|
tangxifan
|
56948244bc
|
[Tool] Patch a critical bug in pb pin fixup
|
2021-04-22 16:19:54 -06:00 |
|
tangxifan
|
96ce6b545f
|
[Tool] Patch repack to consider design constraints for pins that are not equivalent
|
2021-04-21 13:53:08 -06:00 |
|
tangxifan
|
0aec30bac6
|
[Tool] Update FPGA core engine to support mux default path overloading through bitstream setting file
|
2021-04-19 15:53:33 -06:00 |
|
tangxifan
|
0b49c22682
|
[Tool] Now Verilog testbench generator support adding dedicated stimuli for reset signals from benchmarks
|
2021-04-18 16:11:11 -06:00 |
|
tangxifan
|
6550ea3dfa
|
[Tool] Rework pin constarint API to avoid expose raw data to judge for developers
|
2021-04-18 12:02:49 -06:00 |
|
tangxifan
|
6e9b24f9bf
|
[Tool] Patch the invalid pin constraint net name
|
2021-04-17 19:56:30 -06:00 |
|
tangxifan
|
253422e7b7
|
[Tool] Bugfix due to refactoring
|
2021-04-17 19:27:03 -06:00 |
|
tangxifan
|
02ca51d84b
|
[Tool] Reorganize functions in full testbench generator to avoid big-chunk codes
|
2021-04-17 17:45:50 -06:00 |
|
tangxifan
|
d95a1e2776
|
[Tool] Encapulate search function in PinConstraint data structure
|
2021-04-17 17:31:55 -06:00 |
|
tangxifan
|
da619fabe7
|
[Tool] FPGA-Verilog testbench generator accepts pin constraints in full testbench
|
2021-04-17 17:19:34 -06:00 |
|
tangxifan
|
6e1b58f8a6
|
[Tool] Update FPGA-Verilog testbench generator to accept pin constraints to non-clock global ports
|
2021-04-17 15:05:22 -06:00 |
|
tangxifan
|
7c6e000be8
|
[Tool] bug fix
|
2021-04-10 15:36:02 -06:00 |
|
tangxifan
|
03b68a1fdd
|
[Tool] Reworked fabric bitstream XML writer to consider multiple configuration regions
|
2021-04-10 15:25:39 -06:00 |
|
tangxifan
|
934918d9c0
|
[Tool] Reworked fabric bitstream output file in plain text format; Support multiple regions
|
2021-04-10 15:06:53 -06:00 |
|
tangxifan
|
4b8f5f294a
|
[Tool] Capsulate fabric bitstream organization for configuration chain
|
2021-04-10 14:28:31 -06:00 |
|
tangxifan
|
afa0e751da
|
[Tool] Use alias for complex bitstream data types
|
2021-04-10 14:12:02 -06:00 |
|
tangxifan
|
902c4cf9e9
|
Merge branch 'master' into dev
|
2021-03-18 15:14:14 -06:00 |
|
tangxifan
|
3ef292bdbb
|
Merge branch 'netlist_name_patch' of https://github.com/LNIS-Projects/OpenFPGA into netlist_name_patch
|
2021-03-17 20:28:40 -06:00 |
|
tangxifan
|
fa11410425
|
[Tool] Remove exceptions on outputing verilog port with lsb=0
|
2021-03-17 20:27:08 -06:00 |
|
tangxifan
|
62a846197b
|
Merge branch 'master' into dev
|
2021-03-15 10:06:34 -06:00 |
|
tangxifan
|
87006e1374
|
Merge branch 'master' into netlist_name_patch
|
2021-03-15 10:06:24 -06:00 |
|
tangxifan
|
024aa5cbe4
|
Merge branch 'master' into dev
|
2021-03-15 09:13:18 -06:00 |
|
tangxifan
|
d2fbda4070
|
Merge branch 'master' into netlist_name_patch
|
2021-03-15 09:13:04 -06:00 |
|
tangxifan
|
b080bcf018
|
Merge branch 'master' into ganesh_dev
|
2021-03-15 09:12:50 -06:00 |
Maciej Kurc
|
02967f2870
|
Added writing rr graph node indices to GSB dump.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
|
2021-03-15 09:28:38 +01:00 |
|
tangxifan
|
c8d41b4e69
|
[Tool] Change routing module port naming to include architecture port names
|
2021-03-14 19:35:49 -06:00 |
|
tangxifan
|
956b9aca01
|
[Tool] Trim dead codes in port naming function
|
2021-03-13 20:23:08 -07:00 |
|
tangxifan
|
2c5634ee76
|
[Tool] Change pin naming of grid modules to be related to architecture port names
|
2021-03-13 20:05:18 -07:00 |
|
tangxifan
|
07257d0ff0
|
[Tool] Patch wrong paths in FPGA-SDC
|
2021-03-13 10:58:03 -07:00 |
|
tangxifan
|
d877a02534
|
[Tool] Patch the extended bitstream setting support on mode-select bits
|
2021-03-10 21:28:09 -07:00 |
|
tangxifan
|
85640a7403
|
[Tool] Extend bitstream setting to support mode bits overload from eblif file
|
2021-03-10 20:45:48 -07:00 |
|
tangxifan
|
e34380a654
|
Merge branch 'master' into default_net_type
|
2021-03-01 08:38:58 -07:00 |
|
tangxifan
|
521e1850c8
|
[Tool] Correct syntax errors for timing definition in verilog for iverilog 10.1
|
2021-02-28 17:04:27 -07:00 |
|
tangxifan
|
73461971d2
|
[Tool] Bug fix for printing single-bit ports in Verilog netlists
|
2021-02-28 16:12:57 -07:00 |
|
tangxifan
|
15e26a5602
|
[Tool] Support default_net_type Verilog syntex in fabric generator
|
2021-02-28 11:57:40 -07:00 |
|
tangxifan
|
df7b436ac7
|
[Tool] Patch repacker to support duplicated nets due to adder nets
|
2021-02-23 19:01:18 -07:00 |
|
tangxifan
|
e6091fb3ff
|
[Tool] Now throw fatal error on mismatch in configurable regions between fabric key and architecture definition
|
2021-02-18 21:56:30 -07:00 |
|
tangxifan
|
a5b8b2a64a
|
[Tool] Use dedicated function to identify wire LUT created by repacker
|
2021-02-18 19:37:44 -07:00 |
|
tangxifan
|
aae03482f5
|
[Tool] Bug fix for wire LUT identification by repacker. Create a dedicated function to identify these LUTs and store the results in shared database
|
2021-02-18 19:37:17 -07:00 |
|
tangxifan
|
61012897cd
|
[Tool] Bug fix for truth table creation for wired LUT created by repacking algorithm
|
2021-02-17 15:31:20 -07:00 |
|
tangxifan
|
af4cc117fb
|
[Tool] bug fix in spypad lut
|
2021-02-09 22:53:18 -07:00 |
|
tangxifan
|
6a0f4f354f
|
[Tool] Support superLUT circuit model in core engine
|
2021-02-09 20:23:05 -07:00 |
|
tangxifan
|
0c409b5bcc
|
[Tool] Add bitstream annotation support
|
2021-02-01 20:49:36 -07:00 |
|
tangxifan
|
f102e84497
|
[Tool] Add bitstream setting file to openfpga library
|
2021-02-01 17:43:46 -07:00 |
|
tangxifan
|
4b77a3a574
|
[Tool] Now activity file is not a manadatory input of openfpga tools
|
2021-01-29 11:33:40 -07:00 |
|
tangxifan
|
d9fda31a9f
|
[Tool] Add --version to openfpga shell option and a command to openfpga shell
|
2021-01-27 16:03:46 -07:00 |
|
tangxifan
|
fd0e73a9bb
|
[Tool] Enhance return code for openfpga shell
|
2021-01-24 14:48:27 -07:00 |
|
tangxifan
|
8cac3291cb
|
[Tool] Add batch mode to openfpga shell execution
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2021-01-24 14:33:58 -07:00 |
ganeshgore
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d502410b40
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Merge pull request #179 from lnis-uofu/unused_gpout_patch
Avoid to output initial signal for general-purpose output ports of FPGA fabrics in Verilog testbenches
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2021-01-23 18:27:54 -07:00 |
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tangxifan
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4cc8b08a6c
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[Tool] Add openfpga version display
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2021-01-23 16:38:00 -07:00 |
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tangxifan
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d2defebee9
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[Tool] Avoid to output initial signal for general-purpose output ports of FPGA fabrics in Verilog testbenches
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2021-01-22 16:42:13 -07:00 |
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tangxifan
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3f80a26172
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[Tool] Bug fix for combinational benchmarks in pre-config testbench generation
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2021-01-19 18:22:50 -07:00 |
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tangxifan
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75b99b78e9
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[Tool] Now testbench generator consider pin constraints in generating clock sources for benchmarks
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2021-01-19 17:38:51 -07:00 |
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tangxifan
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da200658c1
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[Tool] Now autocheck top testbench consider pin constraints to generate operating clock sources for benchmarks
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2021-01-19 17:29:59 -07:00 |
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tangxifan
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0670c2de59
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[Tool] Deploy pin constraints to preconfig Verilog module generation
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2021-01-19 16:56:30 -07:00 |
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tangxifan
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8c311b8282
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[Tool] Bug fix in repacker for considering design constraints
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2021-01-17 12:26:14 -07:00 |
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tangxifan
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2efe513122
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[Tool] Now repack consider design constraints; test pending
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2021-01-16 21:57:17 -07:00 |
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tangxifan
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bb8e7e25c2
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[Tool] Start deploying design constraints in repack engine
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2021-01-16 21:27:12 -07:00 |
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tangxifan
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fa67517349
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[Tool] Add repack design constraints to openfpga command 'repack'
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2021-01-16 18:49:34 -07:00 |
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tangxifan
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ad7a54db1b
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[Tool] Add repack dc library to compilation
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2021-01-16 17:20:59 -07:00 |
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tangxifan
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87b2c1f3b8
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[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation
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2021-01-15 12:01:53 -07:00 |
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tangxifan
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852f5bb72e
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[Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers
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2021-01-14 15:38:24 -07:00 |
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tangxifan
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9cc9e45b4b
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[Tool] Apply a dirty fix to Verilog testbench generator so that multi-clock testbench can be generated
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2021-01-13 15:13:19 -07:00 |
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tangxifan
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c0da6b900a
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[Tool] Bug fix in creating multi-bit clock port connections
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2021-01-12 18:38:00 -07:00 |
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tangxifan
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65b2fe3ab7
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[Tool] Bug fix in the global tile connection by considering all the subtiles
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2021-01-10 11:52:38 -07:00 |
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tangxifan
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9a441fa5cc
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[Tool] Upgrade openfpga to support extended global tile port definition
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2021-01-09 18:47:12 -07:00 |
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tangxifan
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cde26597ed
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[Tool] Bug fix in scan chain builder calling
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2021-01-04 18:45:47 -07:00 |
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tangxifan
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804b721a19
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[Tool] Bug fix in the configuration chain connection builder
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2021-01-04 17:41:29 -07:00 |
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tangxifan
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bfd305b5a5
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[Tool] Patch the bug in finding data output ports for CCFF
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2021-01-04 17:22:30 -07:00 |
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tangxifan
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cc91a0aebd
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[Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder
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2021-01-04 17:14:26 -07:00 |
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tangxifan
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d11a3d9fef
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[Tool] Avoid outputting signal initialization codes because they are bulky
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2020-12-06 14:29:16 -07:00 |
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tangxifan
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cb2bd2e31c
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[Tool] Remove register ports for mini local encoders (1-bit data out)
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2020-12-06 14:21:54 -07:00 |
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tangxifan
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6bdfcb0147
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[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming
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2020-12-05 12:44:09 -07:00 |
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tangxifan
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6f18688f0e
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[Tool] Now routing multiplexer in the same circuit model (regardless or input sizes) can share the same primitive module
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2020-12-05 10:53:01 -07:00 |
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tangxifan
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0da92ad888
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[Tool] Split MUX Verilog netlist into two separated files: one contains only primitives while the other contains the top-level modules
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2020-12-04 22:16:51 -07:00 |
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tangxifan
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5be9e9b736
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[Tool] Adapted tools to support I/O in center grid
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2020-12-04 18:50:13 -07:00 |
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tangxifan
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73aaa261d8
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[Tool] Relax the IO restriction in pb_pin post-routing packing fix-up
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2020-12-04 17:55:25 -07:00 |
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tangxifan
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4aa6264b1c
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[Tool] Rework simulation time period to be sync with actual stimuli
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2020-12-02 22:58:13 -07:00 |
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tangxifan
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b661c39b04
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[Tool] Force the number of simulation clock cycles to be >= 2 to avoid false-positive self-testing in testbenches
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2020-12-02 19:36:36 -07:00 |
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tangxifan
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3a708cff21
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[Tool] Bug fix to enable nature fracturable LUT design
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2020-11-25 23:01:18 -07:00 |
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tangxifan
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c82f01b3ab
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[Tool] Use conditional operator in signal initialization to eliminate all the warning messages
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2020-11-23 15:50:23 -07:00 |
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tangxifan
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e644545f21
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[Doc] Remove signal initialization for select ports of MUXes and Pass-gates; Use urandom to generate just-fit random vectors
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2020-11-23 15:02:06 -07:00 |
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tangxifan
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3b2a4c5387
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[Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists
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2020-11-22 20:25:03 -07:00 |
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tangxifan
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57a24570f5
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[Tool] Move icarus and signal initialization options to testbench generator
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2020-11-22 16:01:31 -07:00 |
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tangxifan
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3f91b8433e
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[Tool] Change the i/o numbering to the clockwise sequence
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2020-11-13 15:00:25 -07:00 |
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tangxifan
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088198c861
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[Tool] enhance error checking in fabric key parser
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2020-11-13 10:56:00 -07:00 |
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tangxifan
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372fb261fd
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[Tool] Extend the support on global tile port for I/O tiles
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2020-11-11 15:09:40 -07:00 |
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tangxifan
|
e627b6dd5d
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[Tool] Enhance port attribute checks in tile annotation data structure
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2020-11-11 13:41:05 -07:00 |
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tangxifan
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9cbc374b33
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[Tool] Add check codes for tile annotation
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2020-11-11 12:03:13 -07:00 |
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tangxifan
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81e56d45d6
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[Tool] Update FPGA-SDC to use the new data structure for global ports
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2020-11-10 21:17:17 -07:00 |
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tangxifan
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c61ec5a8b8
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[Tool] Bug fix for defining global ports from tiles
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2020-11-10 20:31:14 -07:00 |
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tangxifan
|
dcb50e4f19
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[Tool] Use use standard data structure to store global port information
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2020-11-10 19:07:28 -07:00 |
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tangxifan
|
cbb1545ee3
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[Tool] Add connection builder for tile global ports to top-level module
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2020-11-10 16:59:00 -07:00 |
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tangxifan
|
5fe9c27600
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[Tool] Remove redundant assertation
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2020-11-09 09:42:39 -07:00 |
|
tangxifan
|
ba0120bd76
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[Tool] Remove the limitation on requiring Qb ports for CCFF
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2020-11-06 11:10:04 -07:00 |
|
tangxifan
|
9b0617ffe6
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[Tool] Bug fix for mappable I/O support
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2020-11-04 20:45:51 -07:00 |
|
tangxifan
|
37c10f0cb5
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[Tool] Add mappable I/O support and enhance I/O support
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2020-11-04 20:21:49 -07:00 |
|
tangxifan
|
4a2874b2bc
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[Tool] Refactor the codes for walking through io blocks
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2020-11-03 13:21:50 -07:00 |
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tangxifan
|
1e47203c7c
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[Tool] Auto-generated gate Verilog netlist should not contain any signal initalization
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2020-11-02 18:35:26 -07:00 |
|
tangxifan
|
e4d974c5c8
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[Tool] Split io location mapping builder from fabric builder
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2020-11-02 18:27:34 -07:00 |
|
tangxifan
|
1fd899ecee
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[Tool] Relex logic block checking codes to skip zero-capacity nodes
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2020-11-02 16:57:19 -07:00 |
|
tangxifan
|
6b25cf720d
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[Tool] Comment on the memory efficiency on fabric bitstream address storage
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2020-10-30 22:09:48 -06:00 |
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tangxifan
|
b78f8bec16
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[Tool] Bug fixed for multi-region configuration frame
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2020-10-30 21:19:20 -06:00 |
|
tangxifan
|
5bcd559851
|
[Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification
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2020-10-30 17:29:04 -06:00 |
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tangxifan
|
0d77916041
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[Tool] Support multi-region frame-based configuration protocol
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2020-10-30 10:43:11 -06:00 |
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tangxifan
|
8ef6ae32fb
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[Tool] Bug fix for bitstream estimator due to the current special status of frame-based protocol
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2020-10-29 17:35:55 -06:00 |
|
tangxifan
|
987eccf586
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[Tool] Bug fix in multi-region memory bank; Basic test passed
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2020-10-29 16:26:45 -06:00 |
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tangxifan
|
448e88645a
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[Tool] Support multiple memory banks in top-level module
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2020-10-29 12:42:03 -06:00 |
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tangxifan
|
bd49ea95d4
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[Tool] Add function to comput configuration bits by region
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2020-10-28 12:37:09 -06:00 |
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tangxifan
|
446f982410
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[Tool] Add warning when number of regions defined in fabric key is different than architecture
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2020-10-28 11:43:05 -06:00 |
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tangxifan
|
1ef0898f41
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[Tool] Now users can specify a different fabric netlist when generating Verilog testbench
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2020-10-12 12:31:51 -06:00 |
|
tangxifan
|
721bcce373
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[Tool] Change analysis SDC file name to track netlist name
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2020-10-10 17:43:35 -06:00 |
|
tangxifan
|
e0d7bcfa11
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[Tool] Bug fix for region-based fabric bitstream using memory bank and frame-based protocols
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2020-09-29 12:49:32 -06:00 |
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tangxifan
|
e988e35f81
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[Tool] Support region-based bitstream in fabric bitstream data base and Verilog testbenches
|
2020-09-29 12:22:10 -06:00 |
|
tangxifan
|
180d72f3e5
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[Tool] Add regions to fabric bitstream
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2020-09-28 21:04:08 -06:00 |
|
tangxifan
|
e179a58b15
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[OpenFPGA Tool] Bug fix for long runtime
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2020-09-28 20:42:18 -06:00 |
|
tangxifan
|
47f3c79927
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[OpenFPGA Tool] Bug fix in module manager due to configurable regions
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2020-09-28 19:08:19 -06:00 |
|
tangxifan
|
f93d46a870
|
[OpenFPGA Tool] Add multiple configuration chain support in top module builder
|
2020-09-28 19:03:19 -06:00 |
|
tangxifan
|
552dddffd0
|
[OpenFPGA Tool] Support configurable regions in module manager
|
2020-09-28 18:13:07 -06:00 |
|
tangxifan
|
052b8b71c7
|
[OpenFPGA Tool] Bug fix in the XML parser for fabric regions
|
2020-09-27 20:54:58 -06:00 |