tangxifan
|
2a5bffa6b9
|
[engine] developing pcf2place integration to openfpga
|
2022-07-28 10:30:43 -07:00 |
|
tangxifan
|
27fea8bbbe
|
[lib] Merge librepackdc into libpcf
|
2022-07-26 15:54:32 -07:00 |
taoli4rs
|
cfc0d08060
|
Add constrain_pin_location command in openfpga; add full flow test.
|
2022-07-20 11:51:00 -07:00 |
|
tangxifan
|
38601f325b
|
[Engine] Add bus group to OpenFPGA core
|
2022-02-17 17:28:55 -08:00 |
|
tangxifan
|
0670c2de59
|
[Tool] Deploy pin constraints to preconfig Verilog module generation
|
2021-01-19 16:56:30 -07:00 |
|
tangxifan
|
ad7a54db1b
|
[Tool] Add repack dc library to compilation
|
2021-01-16 17:20:59 -07:00 |
|
tangxifan
|
4f8260a7ba
|
remove obselete codes and update regression tests
|
2020-07-04 17:31:34 -06:00 |
|
tangxifan
|
675a59ecb8
|
Move fpga_bitstream to the libopenfpga library and add XML reader
|
2020-06-20 18:25:17 -06:00 |
|
tangxifan
|
3499b4d3e7
|
add fabric key writer for top-level module
|
2020-06-12 10:41:34 -06:00 |
|
tangxifan
|
65c81e14b2
|
add simulation ini file writer
|
2020-02-27 18:01:47 -07:00 |
|
tangxifan
|
523f9ac391
|
start implement openfpga shell and use vpr as a macro
|
2020-01-22 20:20:10 -07:00 |