tangxifan
|
3cf7950bc1
|
add wire module generation and simplify Verilog generation for wires
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2019-10-21 20:20:34 -06:00 |
|
tangxifan
|
c076da9bab
|
remove redundant codes
|
2019-10-21 18:48:34 -06:00 |
|
tangxifan
|
81093f0db6
|
add lut module generation and simplify Verilog generation codes
|
2019-10-21 17:54:15 -06:00 |
|
tangxifan
|
f002f7e30f
|
add const 0 and 1 module Verilog generation
|
2019-10-21 14:17:09 -06:00 |
|
tangxifan
|
bd37f0d542
|
correct bugs in decoder data port alignment to memory ports of multiplexing structure
|
2019-10-21 13:16:15 -06:00 |
|
tangxifan
|
fe433f3e50
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bug fixed for local encoders and module nets creation
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2019-10-21 12:23:00 -06:00 |
|
tangxifan
|
b2f57ecf81
|
plug in MUX module graph generation, still local encoders contain dangling net, bug fixing
|
2019-10-21 00:00:30 -06:00 |
|
tangxifan
|
520e145af2
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move mux_lib to fpga_x2p_setup
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2019-10-19 19:13:52 -06:00 |
|
tangxifan
|
04f0fbebf7
|
plug in module graph to feed verilog writers
|
2019-10-18 21:59:22 -06:00 |
|
tangxifan
|
b1cafcdbde
|
add missing files
|
2019-10-18 21:04:35 -06:00 |
|
tangxifan
|
fbe56a06c4
|
add decoder module builders
|
2019-10-18 21:01:10 -06:00 |
|
tangxifan
|
7c1bce4b59
|
add module builders for essential gates
|
2019-10-18 20:41:05 -06:00 |
|
tangxifan
|
3b82d62d03
|
start developing module graph builders
|
2019-10-18 20:02:02 -06:00 |
|
tangxifan
|
db38f21412
|
add netlist manager class
|
2019-10-18 17:59:03 -06:00 |
|
tangxifan
|
8c1158fc5c
|
refactor memory organization at the top-level module
|
2019-10-18 15:33:25 -06:00 |
|
tangxifan
|
cfec8d70ab
|
improved refactoring on clb2clb connection by considering flexible arch
|
2019-10-18 11:20:09 -06:00 |
|
tangxifan
|
4171a674b1
|
refactored clb2clb direct connects for cross-column/row
|
2019-10-17 23:06:59 -06:00 |
|
tangxifan
|
190449c06f
|
refactoring top-level module with clb2clb direct connection
|
2019-10-17 17:29:04 -06:00 |
|
tangxifan
|
945e138e62
|
debugged the gsb-grid connection in top module.
|
2019-10-15 22:02:25 -06:00 |
|
tangxifan
|
c9d8311a93
|
bug fixing for grid-gsb connections in top module when using compact routing
|
2019-10-15 18:00:55 -06:00 |
|
tangxifan
|
6a13120208
|
rename grid modules to be clear
|
2019-10-15 16:28:46 -06:00 |
|
tangxifan
|
071757dc52
|
add module nets to connect grids and sbs
|
2019-10-15 16:08:51 -06:00 |
Ganesh Gore
|
c034b871bb
|
Made activity file independent of power option
|
2019-10-15 16:08:25 -06:00 |
|
Ganesh Gore
|
eaf8ecee86
|
added _vpr.txt subscript to vpr log files
|
2019-10-15 16:07:34 -06:00 |
|
tangxifan
|
4b56b755f2
|
refactored instanciation of routing modules in top module
|
2019-10-14 21:06:10 -06:00 |
|
tangxifan
|
bd6a0c6a55
|
refactored grid instance addition to top module
|
2019-10-14 17:47:10 -06:00 |
|
tangxifan
|
f779ad7ecf
|
bug fixing for global and gpio port wiring; start refactoring top-level module
|
2019-10-14 15:53:04 -06:00 |
|
tangxifan
|
6793c67c8d
|
refactored pb_type and grid Verilog generation
|
2019-10-13 21:07:30 -06:00 |
|
tangxifan
|
b581399761
|
add memory ports and nets to intermediate pb_types
|
2019-10-13 17:45:32 -06:00 |
|
tangxifan
|
cab4bd6807
|
add gpio ports to pb_type modules
|
2019-10-13 16:23:22 -06:00 |
|
tangxifan
|
0f50251b3b
|
add mux and associated memory modules in refactoring Verilog generation for pb_types
|
2019-10-13 11:11:19 -06:00 |
|
tangxifan
|
85644d07ae
|
refactoring pb interc Verilog generation
|
2019-10-12 21:55:53 -06:00 |
|
tangxifan
|
a65b76c25a
|
Merge branch 'dev' into refactoring
|
2019-10-12 18:24:03 -06:00 |
|
tangxifan
|
08df0fd585
|
Merge pull request #30 from LNIS-Projects/master
Update README from Tim
|
2019-10-12 11:19:05 -06:00 |
|
tangxifan
|
d1948c82eb
|
Refactoring Verilog generation intermediate level of pb_types and SRAM port generation
|
2019-10-11 21:43:47 -06:00 |
|
tangxifan
|
49a8273482
|
Merge pull request #29 from mithro/patch-1
Small formatting fixes to the README
|
2019-10-11 20:16:56 -06:00 |
|
tangxifan
|
b3ca0d32a4
|
remove configuration bus naming dependency on SRAM circuit models
|
2019-10-11 19:47:36 -06:00 |
|
tangxifan
|
73a5977e0d
|
Debugged Verilog generation for primitive pb_types
|
2019-10-11 18:00:37 -06:00 |
|
tangxifan
|
50f7d1eae3
|
bug fixing in Verilog port merging and instanciation
|
2019-10-11 14:20:04 -06:00 |
|
tangxifan
|
663b1b7665
|
refactorint net addition for configuration signals in module graph
|
2019-10-11 13:07:14 -06:00 |
|
tangxifan
|
c9950162d1
|
start plug in new Verilog writer. Start debugging
|
2019-10-10 22:02:46 -06:00 |
|
tangxifan
|
1f650aac73
|
add local direct connection Verilog code generation
|
2019-10-10 20:54:31 -06:00 |
Tim Ansell
|
916cfa27ed
|
Small formatting fixes to the README
* Make the compile steps easy to copy.
* Small wording fixes.
* Use relative links (github rewrites them).
* Remove unneeded `<br>` tags.
|
2019-10-10 19:39:44 -07:00 |
|
tangxifan
|
f2b3341d87
|
developing verilog writer for generic module graph
|
2019-10-10 20:09:55 -06:00 |
|
tangxifan
|
e5956467fd
|
developing verilog writer for modules
|
2019-10-10 14:43:32 -06:00 |
|
tangxifan
|
edad988ebb
|
add net accessor and mutators to module manager
|
2019-10-09 21:14:30 -06:00 |
|
tangxifan
|
557d8b60f3
|
start implementing module graph-based connection
|
2019-10-09 20:30:16 -06:00 |
|
tangxifan
|
9cb6e64ab3
|
refactoring instanciation inside primitive pb_type Verilog module
|
2019-10-08 21:29:42 -06:00 |
|
tangxifan
|
6f42aac626
|
add wire connection in Verilog module declaration
|
2019-10-08 20:14:38 -06:00 |
|
tangxifan
|
6bed89c237
|
refactored counting config bits for circuit model and update Verilog generation for primitive pb_types
|
2019-10-08 18:00:04 -06:00 |