ganeshgore
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d1e260f54f
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Spice related option added
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2019-12-30 12:16:04 -07:00 |
tangxifan
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ef9ed2ccbc
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added duplicate_grid_pin test case
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2019-12-26 15:08:31 -07:00 |
AurelienUoU
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09fd2afa9c
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Adding heterogeneous synthesis requirements
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2019-12-03 16:09:26 -07:00 |
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AurelienUoU
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32176eb352
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Adding EPFL benchmark task for openfpga_flow
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2019-12-03 14:31:53 -07:00 |
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AurelienUoU
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2f14716f13
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Adding DPRAM behavioural Verilog netlist and its TB
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2019-12-03 13:58:20 -07:00 |
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tangxifan
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96733f9ea8
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add minor comments in task file for modelsim regression tests
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2019-11-16 22:34:03 -07:00 |
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Ganesh Gore
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3f235a16f9
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2019-11-16 19:14:34 -07:00 |
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Ganesh Gore
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6bb11918dc
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Updated modelsim and collected result
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2019-11-16 19:10:04 -07:00 |
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tangxifan
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a13f406918
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tweaking mcnc_big20 task run for modelsim
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2019-11-16 18:00:55 -07:00 |
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Ganesh Gore
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00ec36c1af
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Added Modelsim error check in log
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2019-11-16 13:18:13 -07:00 |
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Ganesh Gore
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373dbe0718
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First draft for multithreaded Modelsim simulation
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2019-11-16 01:06:09 -07:00 |
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Ganesh Gore
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f05aede868
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Added task support for modelsim script
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2019-11-15 23:23:15 -07:00 |
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Ganesh Gore
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f52eaef622
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Updated flow script and skipped travis upload on failure test setup.
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2019-11-15 14:35:15 -07:00 |
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tangxifan
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4df6402241
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add python script for batch simulations
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2019-11-15 14:23:03 -07:00 |
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tangxifan
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d391983e8c
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passing regression test on dpram benchmarks
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2019-11-07 14:57:46 -07:00 |
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tangxifan
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56b4ee008e
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add test for heterogeneous FPGA and fix bugs
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2019-11-06 17:45:11 -07:00 |
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tangxifan
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4ea5756be6
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bug fixed for std cell MUX2 architecture and add the case to regression tests
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2019-11-06 16:06:47 -07:00 |
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tangxifan
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09eb373a6e
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bug fixing for autocheck top testbench where clock port is not default names
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2019-11-06 12:21:20 -07:00 |
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tangxifan
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00280b835e
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reorganize regression tests
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2019-11-05 16:31:42 -07:00 |
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tangxifan
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7952d134b9
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add tree-like mux test case to regression test
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2019-11-05 16:24:39 -07:00 |
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tangxifan
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a308a13d7c
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use prefix instead of lib_name when building modules, then use lib_name for standard cell modules
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2019-11-05 15:41:59 -07:00 |
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tangxifan
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0ec465d4e1
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refactoring auto-check top Verilog testbench
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2019-11-03 17:41:29 -07:00 |
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tangxifan
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dc241e6c03
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add explicit port mapping support in testbenches; remove dangling ports in benchmarks
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2019-11-02 23:03:47 -06:00 |
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Ganesh Gore
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a880802803
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Bug Fix: Corrected read VPR stat filename
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2019-11-01 20:51:05 -06:00 |
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tangxifan
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e2b042c61c
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Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
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2019-11-01 18:27:27 -06:00 |
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Ganesh Gore
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370a5ed408
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Bug Fix: shifter ff.v include path to tcl script
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2019-11-01 18:22:40 -06:00 |
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Ganesh Gore
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595d2d3070
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Simple argument shuffle
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2019-11-01 18:21:26 -06:00 |
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Ganesh Gore
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27005d6640
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Added Modelsim Python Script
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2019-11-01 18:20:40 -06:00 |
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tangxifan
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49bfb3223c
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add compact routing to regression test
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2019-11-01 10:53:47 -06:00 |
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tangxifan
|
531cc064fc
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bug fixing for formal top-level testbench
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2019-11-01 10:47:40 -06:00 |
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Ganesh Gore
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da0778e813
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Merge remote-tracking branch 'lnis_origin/refactoring' into ganesh_dev
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2019-11-01 00:46:34 -06:00 |
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tangxifan
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d709868463
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adding more regression tests which is quick run but very helpful for debugging
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2019-10-31 20:17:40 -06:00 |
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tangxifan
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a6a3e7c36b
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adding mcnc_big20 to regression test
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2019-10-31 19:31:27 -06:00 |
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Ganesh Gore
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81180939ca
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Bug fix: Missing exit_if_fail flag in fpga_flow script
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2019-10-31 09:56:57 -06:00 |
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tangxifan
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5531422186
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update regression test with no-explicit port mapping cases
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2019-10-30 19:37:06 -06:00 |
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tangxifan
|
55fbd72293
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many bugs have been fixed
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2019-10-30 15:50:42 -06:00 |
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tangxifan
|
4398cffaaa
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single mode is working, multi-mode is under debugging
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2019-10-29 22:32:36 -06:00 |
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tangxifan
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10491c4291
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bring single mode test case online with bug fixing
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2019-10-28 17:04:10 -06:00 |
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tangxifan
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5cb3717433
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add single mode test case to regression test. debugging now
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2019-10-28 15:57:17 -06:00 |
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Ganesh Gore
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c034b871bb
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Made activity file independent of power option
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2019-10-15 16:08:25 -06:00 |
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Ganesh Gore
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eaf8ecee86
|
added _vpr.txt subscript to vpr log files
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2019-10-15 16:07:34 -06:00 |
Baudouin Chauviere
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027272c976
|
Faster regression test
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2019-10-05 12:10:55 -06:00 |
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Baudouin Chauviere
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db059af8b8
|
Lighten the regression test
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2019-10-03 13:33:28 -06:00 |
|
Baudouin Chauviere
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c7e1f7d90b
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Added explicit_verilog to regression test in a clean way
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2019-10-03 10:17:04 -06:00 |
|
Baudouin Chauviere
|
33e50bbc8c
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fix
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2019-10-01 16:54:16 -06:00 |
|
Baudouin Chauviere
|
7c3ab38410
|
Hot fix
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2019-10-01 16:40:16 -06:00 |
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Ganesh Gore
|
069f628bb0
|
Merge branch 'dev' of github.com:LNIS-Projects/OpenFPGA into ganesh_dev
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2019-09-28 11:21:37 -06:00 |
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Ganesh Gore
|
d269472daf
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Updated formality python script
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2019-09-27 14:00:57 -06:00 |
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AurelienUoU
|
feddcbcb21
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-09-23 11:41:38 -06:00 |
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tangxifan
|
5efea159c5
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Simplify part of regression test to min_route_chan_width
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2019-09-22 11:14:33 -06:00 |