tangxifan
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090f483a11
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[Script] Now task-run script support the use of env variables openfpga_path in yosys scripts
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2021-03-16 16:45:57 -06:00 |
Lalit Sharma
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6a1ce01084
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Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS
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2021-03-07 22:02:11 -08:00 |
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Lalit Sharma
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0cbad747a1
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Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family
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2021-03-04 01:10:47 -08:00 |
|
Lalit Sharma
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817729ac86
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Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables
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2021-03-01 22:31:15 -08:00 |
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tangxifan
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a819375f69
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[Script] Bug fix on the run_fpga_flow.py script when power analysis is disabled
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2021-02-16 16:53:13 -07:00 |
Tarachand Pagarani
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3a587f663a
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copy yosys output file in case power analysis setting is off
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2021-02-15 02:36:02 -08:00 |
Ganesh Gore
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6cdc31f073
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[Flow] ACE is optional duign flow script
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2021-02-03 19:07:48 -07:00 |
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Ganesh Gore
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df4a397470
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[Cleanup] Removed deadcode
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2021-02-03 10:35:14 -07:00 |
|
ganeshgore
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289d9d2169
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[Bugfix] Honors yosys_tmpl parameter in flow script
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2020-12-03 12:24:24 -07:00 |
|
ganeshgore
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59bd7d0f18
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[Flow] Changed substitute to safe_sustitute option
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2020-11-25 22:09:36 -07:00 |
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ganeshgore
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fefba0db59
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Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev
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2020-11-25 17:29:53 -07:00 |
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ganeshgore
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1554f583b7
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[Flow] Now support explicit variable file for task
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2020-11-25 17:22:41 -07:00 |
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tangxifan
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521accdc88
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Merge pull request #104 from lukefahr/disp_fix
FLOW: fixed display flag
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2020-10-07 09:54:06 -06:00 |
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tangxifan
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7b12c28e4f
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Merge pull request #102 from lukefahr/blif_bug
Fixed blif formatting bug
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2020-10-06 20:05:02 -06:00 |
Andrew Lukefahr
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33bbe0ec48
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FLOW: fixed display flag
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2020-10-06 20:52:28 -04:00 |
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Andrew Lukefahr
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d68427e47b
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Fixed blif formatting bug
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2020-10-06 20:46:50 -04:00 |
|
Andrew Lukefahr
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2d92a1f1af
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Edits to enable basic run_fpga_flow.py
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2020-10-02 10:18:10 -04:00 |
|
ganeshgore
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747c062f86
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BugFix : Flow script accepts extra OpenFPGA arguments
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2020-07-27 18:10:43 -06:00 |
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ganeshgore
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3b6cd885f3
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BugFix: Fixed yosys_vpr with openFPGA_Shell
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2020-07-22 11:57:04 -06:00 |
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ganeshgore
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41585436c8
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Added external_fabric_key_file key
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2020-06-12 15:37:12 -06:00 |
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ganeshgore
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c1b73efa62
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Added support for simulation setting file in the task flow
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2020-06-10 23:12:30 -06:00 |
|
ganeshgore
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689c4a3e19
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BugFix: The filename in the previous commit
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2020-04-15 12:44:22 -06:00 |
|
ganeshgore
|
7f37bf1441
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Added formal verification support to fpga_flow script
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2020-04-15 12:24:51 -06:00 |
|
ganeshgore
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f6b3c5854a
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Bugfix :
+ OpenFPGA template variables update
+ Default path for the verilog netlist
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2020-04-11 16:45:22 -06:00 |
|
ganeshgore
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8ea272dc2c
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Patched the OpenFPGA shell execution bug
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2020-04-08 21:28:14 -06:00 |
|
ganeshgore
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583a4d8767
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Fixed bug in openfpga_flow script
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2020-04-08 12:04:08 -06:00 |
|
ganeshgore
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ea4122a8a4
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Updated openfpga_flow and task file to support sheel run
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2020-04-06 00:34:36 -06:00 |
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ganeshgore
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d1d3446568
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backedup partial upgrade for fpga_flow script
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2020-04-05 11:36:24 -06:00 |
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ganeshgore
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46bb5ef9d0
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Added disp option in openfpga_flow, Default is --nodisp
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2020-01-23 10:04:38 -07:00 |
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ganeshgore
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f0bed1244c
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Added blif file folding before VPR run
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2020-01-09 16:50:34 -07:00 |
|
ganeshgore
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74b650e9e1
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Added fpga_x2p_duplicate_grid_pin option
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2019-12-30 12:25:28 -07:00 |
|
ganeshgore
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d1e260f54f
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Spice related option added
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2019-12-30 12:16:04 -07:00 |
|
Ganesh Gore
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6bb11918dc
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Updated modelsim and collected result
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2019-11-16 19:10:04 -07:00 |
|
Ganesh Gore
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333d10c94c
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Added vpr_fpga_verilog_print_simulation_ini option
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2019-11-15 14:26:57 -07:00 |
|
Ganesh Gore
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a880802803
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Bug Fix: Corrected read VPR stat filename
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2019-11-01 20:51:05 -06:00 |
|
Ganesh Gore
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595d2d3070
|
Simple argument shuffle
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2019-11-01 18:21:26 -06:00 |
|
Ganesh Gore
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81180939ca
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Bug fix: Missing exit_if_fail flag in fpga_flow script
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2019-10-31 09:56:57 -06:00 |
|
Ganesh Gore
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c034b871bb
|
Made activity file independent of power option
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2019-10-15 16:08:25 -06:00 |
|
Ganesh Gore
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eaf8ecee86
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added _vpr.txt subscript to vpr log files
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2019-10-15 16:07:34 -06:00 |
|
Ganesh Gore
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cd5fd6ce6c
|
Added explicit checking to VVP execution
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2019-09-18 12:14:26 -06:00 |
|
Ganesh Gore
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169732ccc1
|
Added verbose option in VVP output
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2019-09-17 22:09:37 -06:00 |
|
Ganesh Gore
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678e3181ba
|
Made compact_routing_hierarchy options uncond
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2019-09-16 21:22:13 -06:00 |
|
Ganesh Gore
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81b9c5b266
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Added flag for VVP exit code
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2019-09-14 12:35:47 -06:00 |
|
Ganesh Gore
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702a7683a8
|
Ensure strict exit of fpga_flow on error
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2019-09-05 10:23:35 -06:00 |
|
Ganesh Gore
|
f4e99c150a
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resolve missing variable bug
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2019-08-31 21:55:32 -06:00 |
|
Ganesh Gore
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06c0dbb328
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Added docuementation for fpga_flow
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2019-08-31 15:19:34 -06:00 |
|
Ganesh Gore
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02137805c7
|
Added python version check in flow and task scripts
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2019-08-29 22:14:30 -06:00 |
|
Ganesh Gore
|
f558437ae1
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Added task for vpr_blif flow
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2019-08-25 00:23:39 -06:00 |
|
Ganesh Gore
|
6e7de16ad4
|
Solved bug in commnad rearrangement
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2019-08-22 23:41:25 -06:00 |
|
Ganesh Gore
|
77e2a7bca3
|
Added execution time logs in flow script
|
2019-08-22 17:01:38 -06:00 |