tangxifan
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5d9e918d5d
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[ci] enable check C/C++ format on CI
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2022-10-06 18:26:06 -07:00 |
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tangxifan
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afdc071c4c
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[engine] apply code format
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2022-10-06 18:13:33 -07:00 |
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tangxifan
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e2debd2dde
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[engine] add missing header files after coding formatter sorts the include files
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2022-10-06 18:08:57 -07:00 |
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tangxifan
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503b95343d
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Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into code_format
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2022-10-06 17:54:48 -07:00 |
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tangxifan
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2a3417163e
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Merge pull request #833 from lnis-uofu/vtr_dependabot
Enabled dependabot for VTR submodule
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2022-10-06 17:54:31 -07:00 |
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tangxifan
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6d31b319a2
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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tangxifan
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b8c59db9e9
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[script] debugging cmake format
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2022-10-06 17:07:57 -07:00 |
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tangxifan
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d3e374fe57
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[script] debugging make format
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2022-10-06 17:04:30 -07:00 |
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tangxifan
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110b27b3fc
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[script] now top-level makefile can do ``make format`` for C/C++ files
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2022-10-06 16:59:15 -07:00 |
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tangxifan
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6230196c21
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[ci] add C/C++ code format style file
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2022-10-06 16:44:05 -07:00 |
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tangxifan
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4c707d1eae
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[vtr] update vtr
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2022-10-06 14:27:15 -07:00 |
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tangxifan
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608c43d05b
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[ci] enable dependabot for vtr
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2022-10-06 14:26:11 -07:00 |
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tangxifan
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10267500be
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Merge pull request #826 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2022-10-04 16:38:20 -07:00 |
github-actions[bot]
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73b1669a41
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Updated Patch Count
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2022-10-04 23:32:50 +00:00 |
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tangxifan
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46044d5217
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Merge pull request #824 from lnis-uofu/place_rr_graph
Fix a bug where placer does not call tileable rr-graph generator
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2022-10-04 12:08:56 -07:00 |
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tangxifan
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ab53f88c2b
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[test] now use a fixed device layout for the single-mode LUT design testcase
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2022-10-04 10:05:22 -07:00 |
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tangxifan
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3a3877fd08
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[engine] update vtr: fix a bug where placer does not call tileable rr_graph generator
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2022-10-03 21:18:08 -07:00 |
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tangxifan
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b652bc8d51
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Merge pull request #823 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2022-10-03 13:32:01 -07:00 |
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github-actions[bot]
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8b63f93e9f
|
Updated Patch Count
|
2022-10-03 20:29:52 +00:00 |
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tangxifan
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62511f4792
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Merge pull request #822 from lnis-uofu/cmake_flag
New option to bypass version build
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2022-10-03 13:28:56 -07:00 |
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tangxifan
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b26b0ce8d8
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[ci] deploy no version number build test to ci
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2022-10-03 11:48:19 -07:00 |
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tangxifan
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cc6bf85433
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[cmake] now rename version to short 'OPENFPGA_ENABLE_VERSION'
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2022-10-03 11:37:41 -07:00 |
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tangxifan
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a144794ce6
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[cmake] skip custom build on version build with an option
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2022-10-03 11:18:43 -07:00 |
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tangxifan
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81e524cec4
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[CMake] Added a new option 'OPENFPGA_WITH_VERSION_UP_TO_DATE' which allows users to skip version build (by default it remains always on)
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2022-10-03 11:11:21 -07:00 |
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tangxifan
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db7a052a2b
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Merge pull request #820 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2022-10-01 18:59:16 -07:00 |
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github-actions[bot]
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fe26429c86
|
Updated Patch Count
|
2022-10-02 00:04:53 +00:00 |
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tangxifan
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30c5569e0f
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Merge pull request #819 from lnis-uofu/gsb_cout_bug
Fixed a bug where pins for direct connections between programmable blocks appears in GSB/Routing blocks
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2022-10-01 14:59:36 -07:00 |
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tangxifan
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13c819bb28
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[ci] deply new test to ci
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2022-10-01 11:04:08 -07:00 |
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tangxifan
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4eaecde0b9
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[test] add golden netlists to ensure no cout in gsb
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2022-10-01 11:03:13 -07:00 |
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tangxifan
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78f30cf072
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[test] add a new test to track the golden netlists where cout is not in GSB
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2022-09-30 15:38:27 -07:00 |
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tangxifan
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1c7d5a05b4
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[engine] update vtr
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2022-09-30 15:26:59 -07:00 |
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tangxifan
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0d8d8446ee
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[test] fixed a bug where OPIN for direct connection is included in GSB
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2022-09-30 15:24:51 -07:00 |
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tangxifan
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9c5be017bc
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Merge pull request #817 from lnis-uofu/wire_lut_test
Add a new test case to ensure that repack can handle wire lut properly
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2022-09-29 18:23:12 -07:00 |
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tangxifan
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e3a4c311c0
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Merge branch 'master' into wire_lut_test
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2022-09-29 17:10:47 -07:00 |
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tangxifan
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45beb068f7
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Merge pull request #818 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2022-09-29 17:10:29 -07:00 |
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github-actions[bot]
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d496568d3b
|
Updated Patch Count
|
2022-09-30 00:06:56 +00:00 |
|
tangxifan
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088ff1a474
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[script] fixed a bug
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2022-09-29 16:27:03 -07:00 |
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tangxifan
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0565ca7aca
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[script] add missing files
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2022-09-29 16:14:38 -07:00 |
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tangxifan
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a3e7133d63
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Merge branch 'master' into wire_lut_test
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2022-09-29 16:02:18 -07:00 |
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tangxifan
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38aa2d7306
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Merge pull request #816 from lnis-uofu/wire_lut_bug
Now accept the post-routing cluster fixup results from VTR
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2022-09-29 16:02:07 -07:00 |
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tangxifan
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2ed4a60f36
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[arch] reduce clb inputs to force net remapping during routing
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2022-09-29 15:52:30 -07:00 |
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tangxifan
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ce0fbe1765
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[test] fixed a few bugs
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2022-09-29 15:32:31 -07:00 |
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tangxifan
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9bc9b61d35
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[test] fixed a few bugs
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2022-09-29 15:11:30 -07:00 |
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tangxifan
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f5e7ec4dd1
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[test] add a new test case to validate wire lut case
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2022-09-29 14:28:59 -07:00 |
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tangxifan
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df1ae7ba2a
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[benchmark] add a new benchmark to enhance the tests for wire-lut features in repacker
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2022-09-29 14:23:17 -07:00 |
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tangxifan
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f7a02422b5
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[arch] add a new arch to reproduce the wire-lut bug in repacker
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2022-09-29 13:59:08 -07:00 |
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tangxifan
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a111d886cf
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Merge branch 'wire_lut_bug' of github.com:lnis-uofu/OpenFPGA into wire_lut_bug
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2022-09-29 13:40:31 -07:00 |
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tangxifan
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3f8e2ade2e
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[script] update missing scripts required by pb_pin_fixup test cases
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2022-09-29 13:39:46 -07:00 |
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tangxifan
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3b11fcea0a
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Merge branch 'master' into wire_lut_bug
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2022-09-29 11:11:35 -07:00 |
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tangxifan
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58487c7766
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[doc] add more notes about the commmand ``pb_pin_fixup``
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2022-09-29 11:01:07 -07:00 |