taoli4rs
|
cfc0d08060
|
Add constrain_pin_location command in openfpga; add full flow test.
|
2022-07-20 11:51:00 -07:00 |
tangxifan
|
a7e87b9432
|
[FPGA-Bitstream] note limitations
|
2022-05-25 18:38:01 +08:00 |
|
tangxifan
|
ffac5a66e1
|
[FPGA-Bitstream] Now encode address bits to save memory in bitstream database
|
2022-05-25 17:45:08 +08:00 |
|
tangxifan
|
bf1a81fbb5
|
[FPGA-bitstream] add timer to computing intensive functions
|
2022-05-25 14:52:32 +08:00 |
|
tangxifan
|
a20f6eaf06
|
[Engine] Fixed a few bugs
|
2022-04-10 21:29:38 +08:00 |
|
tangxifan
|
755be78b39
|
[Engine] Now GSB output file contains segments name and pin name in SB module
|
2022-04-10 21:22:30 +08:00 |
|
tangxifan
|
6171abdf95
|
[FPGA-Bitstream] Now report_bitstream_distribution includes fabric bitstream stats
|
2022-03-29 19:41:15 +08:00 |
|
tangxifan
|
4d67864c2c
|
[Engine] Now global port can be connected partial pins of a tile port
|
2022-03-20 11:36:03 +08:00 |
|
tangxifan
|
8ab090651a
|
[FPGA-Verilog] Now port/wire names uses "__" to avoid collision with FPGA global ports
|
2022-03-16 20:51:37 +08:00 |
|
tangxifan
|
235887e03a
|
[FPGA-Verilog] Fixed a bug on config-enable signals
|
2022-02-23 22:35:23 -08:00 |
|
tangxifan
|
086642d134
|
[FPGA-Verilog] Now preconfigured wrapper can handle config_enable signals correctly
|
2022-02-23 15:33:24 -08:00 |
|
tangxifan
|
1c18d14ad5
|
[FPGA-Verilog] Add big/little endian support to output ports
|
2022-02-19 09:23:48 -08:00 |
|
tangxifan
|
3e43a60fdc
|
[FPGA-Verilog] Add big/little endian support when instanciate reference benchmarks
|
2022-02-19 09:15:38 -08:00 |
|
tangxifan
|
671188dfa4
|
[FPGA-Verilog] Now support big/little-endian in bus group
|
2022-02-18 23:05:03 -08:00 |
|
tangxifan
|
790715f46a
|
[FPGA-Verilog] Fixing bugs when using bus group in full testbench generator
|
2022-02-18 15:41:35 -08:00 |
|
tangxifan
|
401f673f16
|
[FPGA-Verilog] Streamline codes by using APIs
|
2022-02-18 14:47:36 -08:00 |
|
tangxifan
|
c16ea8d082
|
[FPGA-Verilog] Fixing bugs in naming wires in verilog testbenches
|
2022-02-18 14:34:32 -08:00 |
|
tangxifan
|
a4dc86a33d
|
[FPGA-Verilog] Now output atom block name removal has a dedicated function
|
2022-02-18 14:30:46 -08:00 |
|
tangxifan
|
f5dd89bbd9
|
[FPGA-Verilog] Fixed bugs in preconfigured wrapper generator when bus group is used
|
2022-02-18 14:08:03 -08:00 |
|
tangxifan
|
0d620888ab
|
[FPGA-Verilog] Now instance can output bus ports with all the pins
|
2022-02-18 12:03:26 -08:00 |
|
tangxifan
|
aa375fd7a4
|
[FPGA-Verilog] Fixed a bug due to the use of bus group in testbench generator
|
2022-02-18 11:31:11 -08:00 |
|
tangxifan
|
6da0ede9b0
|
[FPGA-Verilog] Adding bus group support to all Verilog testbench generators
|
2022-02-17 23:48:44 -08:00 |
|
tangxifan
|
c96f0d199d
|
[FPGA-Verilog] Adding bus group support in Verilog testbenches
|
2022-02-17 23:14:28 -08:00 |
|
tangxifan
|
e67f8ad8b2
|
[FPGA-Verilog] Now full testbench does not check any output vectors during configuration phase
|
2022-02-15 17:19:50 -08:00 |
|
tangxifan
|
be8f18310d
|
[FPGA-Verilog] Fix a bug on the polarity of reset signals that drive FPGA instances
|
2022-02-14 17:16:26 -08:00 |
|
tangxifan
|
d3f68db228
|
[FPGA-Verilog] fixing bugs in reset ports for counters in full testbenches
|
2022-02-14 17:00:54 -08:00 |
|
tangxifan
|
34e192c5ca
|
[FPGA-Verilog] Fixed a bug on wiring FPGA global ports
|
2022-02-14 15:21:29 -08:00 |
|
tangxifan
|
8d48492ec0
|
[FPGA-Verilog] Add clock ports to the white list when adding postfix
|
2022-02-14 11:09:00 -08:00 |
|
tangxifan
|
5794561f7b
|
[FPGA-Verilog] Now shared input wire/register has a postfix in full testbench
|
2022-02-14 10:39:27 -08:00 |
|
tangxifan
|
2ca73d79e4
|
[FPGA-Verilog] Fixed the bug on pin constraints
|
2022-02-13 22:08:06 -08:00 |
|
tangxifan
|
b1377f0d34
|
[FPGA-Verilog] Fix syntax errors
|
2022-02-13 20:29:05 -08:00 |
|
tangxifan
|
6e132aace4
|
[FPGA-Verilog] Remove the prefix added by VPR in preconfigured top module
|
2022-02-13 20:26:21 -08:00 |
|
tangxifan
|
fb4106de19
|
[FPGA-Verilog] Fixed a bug in naming mismatch
|
2022-02-13 20:06:35 -08:00 |
|
tangxifan
|
a068237082
|
[FPGA-Verilog] Rename internal wire names in testbenches, in order to be consistent with reference benchmarks
|
2022-02-13 19:55:16 -08:00 |
|
tangxifan
|
1c94d0f285
|
[FPGA-Verilog] Now preconfig testbench generator has a new option ``--use_relative_path``
|
2022-02-01 13:25:09 -08:00 |
|
tangxifan
|
f311a034bb
|
[FPGA-Verilog] Now full testbench generator has a new option ``--use_relative_path``
|
2022-02-01 12:17:02 -08:00 |
|
tangxifan
|
2b8e2de0c9
|
[FPGA-Verilog] Fix bugs
|
2022-01-31 14:23:04 -08:00 |
|
tangxifan
|
6c29c286bc
|
[FPGA-Verilog] Fix a bug which cause errors
|
2022-01-31 14:06:58 -08:00 |
|
tangxifan
|
63f44adf15
|
[FPGA-Verilog] Now have a new option ``--use_relative_path``
|
2022-01-31 12:48:05 -08:00 |
Emin Cetin
|
6c2c4e8b14
|
adding comment
|
2022-01-28 08:57:45 +03:00 |
|
Emin Cetin
|
f9b47c3b34
|
missing semicolon
|
2022-01-27 16:49:04 +03:00 |
|
Emin Cetin
|
8f7ee4e338
|
changing condition of bitstream downloading
|
2022-01-27 11:49:55 +03:00 |
|
tangxifan
|
a9a56686e2
|
[Engine] Add a new option ``--unique`` to command ``write_gsb_to_xml``
|
2022-01-26 11:10:29 -08:00 |
|
tangxifan
|
a9e6b7c12e
|
[FPGA-Bitstream] Remove version numbers when ``--no_time_stamp`` is enabled
|
2022-01-25 20:33:49 -08:00 |
|
tangxifan
|
33064ca4cf
|
[FPGA-SDC] Add a new option ``--no_time_stamp`` to all the commands
|
2022-01-25 15:51:28 -08:00 |
|
tangxifan
|
b09e13b42c
|
[FPGA-Verilog] Fixed a bug on invalid option of a command
|
2022-01-25 13:45:44 -08:00 |
|
tangxifan
|
25143d07f1
|
[FPGA-Bitstream] Now has a new option ``--no_time_stamp`` to all the commands that output bitstream files
|
2022-01-25 13:37:54 -08:00 |
|
tangxifan
|
62b57b05d2
|
[Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp``
|
2022-01-25 12:09:08 -08:00 |
nadeemyaseen-rs
|
dbe8616837
|
Merge remote-tracking branch 'upstream/master' into update_from_upstream
|
2021-12-23 00:00:22 +05:00 |
Tarachand Pagarani
|
02e4ae9740
|
allow bitstream setting on hard blocks
|
2021-12-07 03:42:22 -08:00 |
|
tangxifan
|
ff264c00a2
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
|
2021-10-31 11:51:34 -07:00 |
|
tangxifan
|
91627abe12
|
[FPGA-Verilog] Fixed a bug on the non-inverted reset signal in testbenches when pin constraints are provided
|
2021-10-30 11:53:46 -07:00 |
|
tangxifan
|
6586ea7816
|
[Engine] Bug fix for fabric key writer which errors out when there is no BL/WL banks in the architecture
|
2021-10-11 09:40:02 -07:00 |
|
tangxifan
|
546350ae41
|
[FPGA-Verilog] Revert back to the previous precomputing strategy for shift register clocks
|
2021-10-10 23:19:39 -07:00 |
|
tangxifan
|
b9c540ec3f
|
[Engine] Upgrade fabric key writer to support BL/WL shift register banks
|
2021-10-10 21:14:14 -07:00 |
|
tangxifan
|
202b50c0e3
|
[FPGA-Verilog] Fixed a weird bug which causes totally different results in fixed and auto shift register clock freq; However, this is a dirty fix. Require further study to know why
|
2021-10-10 20:57:23 -07:00 |
|
tangxifan
|
de3275e9ba
|
[FPGA-Verilog] Fixed a critical in verilog testbench which caused the last bit of bitstream skipped when loading to shift register chains
|
2021-10-10 16:56:07 -07:00 |
|
tangxifan
|
1c46a92559
|
[FPGA-Bitstream] Bug fix
|
2021-10-09 21:59:56 -07:00 |
|
tangxifan
|
6aa4991314
|
[FPGA-Verilog] Bug fix
|
2021-10-09 21:34:07 -07:00 |
|
tangxifan
|
7810f376c8
|
[FPGA-Bitstream] Patch code comments
|
2021-10-09 21:03:01 -07:00 |
|
tangxifan
|
34575f7222
|
[FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank
|
2021-10-09 20:39:45 -07:00 |
|
tangxifan
|
aac74d9163
|
[Engine] Bug fix
|
2021-10-09 18:46:20 -07:00 |
|
tangxifan
|
fa08f44107
|
[Engine] Bug fix
|
2021-10-09 16:58:56 -07:00 |
|
tangxifan
|
19a551e641
|
[Engine] Upgrade fabric generator to support multiple shift register banks in a configuration region
|
2021-10-09 16:44:04 -07:00 |
|
tangxifan
|
932beb480a
|
[Engine] Add fast look-up to the shift register bank data structure
|
2021-10-08 22:00:01 -07:00 |
|
tangxifan
|
e3ff40d9e0
|
[Engine] Add missing return value
|
2021-10-08 20:17:55 -07:00 |
|
tangxifan
|
39a69e0d88
|
[Engine] Upgrading fabric generator to support customizable shift register banks from fabric key and configuration protocols
|
2021-10-08 17:58:06 -07:00 |
|
tangxifan
|
8f5f30792f
|
[Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface
|
2021-10-08 15:25:37 -07:00 |
|
tangxifan
|
f7484d4323
|
[Engine] Update the key memory data structure to contain shift register bank general information
|
2021-10-08 10:42:18 -07:00 |
|
tangxifan
|
9693a269ee
|
[FPGA-Bitstream] Now dont' care bits are truelly seen in single-chain and flatten QuickLogic memory bank
|
2021-10-07 11:31:16 -07:00 |
|
tangxifan
|
54a8809b3c
|
[FPGA-Verilog] Bug fix in computing clock frequency for shift register chains
|
2021-10-06 16:49:28 -07:00 |
|
tangxifan
|
27153bbc89
|
[FPGA-Verilog] Bug fix in matching shift register clocks between verilog ports and simulation setting definition
|
2021-10-06 13:38:51 -07:00 |
|
tangxifan
|
bf473f50f8
|
[FPGA-Verilog] Correct bugs in logging clock frequencies
|
2021-10-06 11:55:57 -07:00 |
|
tangxifan
|
fcb5470baa
|
[Lib] Add validator to check if a clock is constrained in simulation settings
|
2021-10-06 11:48:23 -07:00 |
|
tangxifan
|
82ed6b177b
|
[FPGA-Verilog] Now consider clock constraints for BL/WL shift registers
|
2021-10-06 11:39:28 -07:00 |
|
tangxifan
|
2ea9826b17
|
[FPGA-Bitstream] Bug fix in wrong option name
|
2021-10-05 18:58:47 -07:00 |
|
tangxifan
|
ad54c8547e
|
[FPGA-Bitstream] Added an option to ``write_fabric_bitstream`` command to enable outputting don't care bits in bitstream files
|
2021-10-05 18:54:02 -07:00 |
|
tangxifan
|
fdd75c4ec8
|
[FPGA-Bitstream] Enable don't care bit to be outputted in bitstream file for QuickLogic memory banks
|
2021-10-05 17:54:07 -07:00 |
|
tangxifan
|
3efd6840a8
|
[Engine] Bug fix for missing WLR ports in auto-generated shift register banks
|
2021-10-04 16:58:01 -07:00 |
|
tangxifan
|
06b018cfe7
|
[FPGA-Bitstream] Reverse bitstream for shift register due to its FIFO nature
|
2021-10-03 16:05:33 -07:00 |
|
tangxifan
|
2badcb58f2
|
[FPGA-Verilog] Fixed a critical bug in verilog testbench generator for QL memory bank using BL/WL register which causes misalignment in shift register loading
|
2021-10-03 16:04:47 -07:00 |
|
tangxifan
|
28904ff526
|
[Engine] Bug fix on wrong port type for shift register chains
|
2021-10-03 12:31:58 -07:00 |
|
tangxifan
|
756b4c7dc8
|
[FPGA-Verilog] Bug fix in estimating the simulation period for QuickLogic memory bank using BL/WL shift registers
|
2021-10-03 12:11:20 -07:00 |
|
tangxifan
|
3eb601531a
|
[FPGA-Verilog] Many bug fixes
|
2021-10-02 23:39:53 -07:00 |
|
tangxifan
|
d453e6477d
|
[FPGA-Verilog] Bug fix
|
2021-10-02 22:32:57 -07:00 |
|
tangxifan
|
02af633acd
|
[FPGA-Verilog] Fixed several bugs in testbench generator which caused iVerilog errors
|
2021-10-02 22:14:15 -07:00 |
|
tangxifan
|
fa7e168137
|
[FPGA-Verilog] Now testbench generator connects global shift register clocks to FPGA ports
|
2021-10-02 22:08:14 -07:00 |
|
tangxifan
|
76d58ebaa0
|
[FPGA-Verilog] Move clock generator to generic stimuli and shift register clock period is auto tuned by programming clock period
|
2021-10-02 21:48:10 -07:00 |
|
tangxifan
|
54ec74d8d2
|
[FPGA-Verilog] Bug fix in code generator
|
2021-10-02 17:31:37 -07:00 |
|
tangxifan
|
32fc0a1692
|
[FPGA-Verilog] Upgrading verilog testbench generator for QuickLogic memory bank using BL/WL shift register
|
2021-10-02 17:25:27 -07:00 |
|
tangxifan
|
f686dd1f60
|
[FPGA-Bitstream] Do not reverse for now. Previous solution looks correct
|
2021-10-01 23:12:38 -07:00 |
|
tangxifan
|
198517a898
|
[FPGA-Bitstream] Bug fix on bitstream sequence for QuickLogic memory bank using shift registers
|
2021-10-01 19:59:50 -07:00 |
|
tangxifan
|
2de6be44d6
|
[Engine] Fixed a critical bug which causes bitstream wrong for QuickLogic memory bank when fast configuration is enabled
|
2021-10-01 18:27:42 -07:00 |
|
tangxifan
|
477c1cd062
|
[Engine] Fixed a critical bug which causes undriven BL/WLs between shift register banks and child modules at the top-level module
|
2021-10-01 17:38:26 -07:00 |
|
tangxifan
|
977d81679d
|
[Engine] Upgrade check codes for WL CCFF
|
2021-10-01 17:23:10 -07:00 |
|
tangxifan
|
9e5debabe1
|
[FPGA-Bitstream] Enable fast configuration for QuickLogic memory banks
|
2021-10-01 16:23:38 -07:00 |
|
tangxifan
|
4f7ab01bf5
|
[FPGA-Bitstream] Reworked the bitstream writer to dump BL/WL words separately
|
2021-10-01 15:47:13 -07:00 |
|
tangxifan
|
2bd2788e77
|
[Engine] Upgrading testbench generator to support QuickLogic memory bank with shift registers
|
2021-10-01 11:23:40 -07:00 |
|
tangxifan
|
cf96d9ff01
|
[Engine] Add programming shift register clock to internal global port data structure
|
2021-10-01 11:05:31 -07:00 |
|
tangxifan
|
7b010ba0f4
|
[Engine] Support programming shift register clock in XML syntax
|
2021-10-01 11:00:38 -07:00 |
|
tangxifan
|
96828e456a
|
[FPGA-Bitstream] Fixed a critical bug which cause reshaping bitstream wrong
|
2021-09-30 22:07:46 -07:00 |
|
tangxifan
|
4bdff1554d
|
[Engine] Fixed a critical bug which cause BL/WL sharing in shift-register-based memory bank broken
|
2021-09-30 21:20:56 -07:00 |
|
tangxifan
|
33972fc0ec
|
[FPGA-Bitstream] Upgraded bitstream writer to support QuickLogic memory bank using shift registers
|
2021-09-30 21:05:41 -07:00 |
|
tangxifan
|
4526133089
|
[FPGA-Bitstream] Add a new data structure that stores fabric bitstream for memory bank using shift registers
|
2021-09-30 17:01:02 -07:00 |
|
tangxifan
|
43c569b612
|
[FPGA-Bitstream] Encapusulate the data structur storing memory bank fabric bitstream for flatten BL/WL into an object
|
2021-09-30 14:47:21 -07:00 |
|
tangxifan
|
4d8019b7c1
|
[FPGA-Bitstream] Bug fix in bitstream generator for shift-register-based memory bank
|
2021-09-29 22:32:45 -07:00 |
|
tangxifan
|
2d4c200d58
|
[FPGA-Verilog] Now FPGA-Verilog can output shift register bank netlists
|
2021-09-29 20:56:02 -07:00 |
|
tangxifan
|
f456c7e236
|
[Engine] Add a new API to the MemoryBankShiftRegisterBank to access all the unique modules
|
2021-09-29 20:34:25 -07:00 |
|
tangxifan
|
b87b7a99c5
|
[Engine] Add MemoryBankShiftRegisterBanks to openfpga context because their contents are required by netlist writers as well as bitstream generators
|
2021-09-29 20:21:46 -07:00 |
|
tangxifan
|
8f0ae937bc
|
[Engine] Upgraded fabric generator to support single shift register bank per configuration region for QuickLogic memory bank
|
2021-09-29 16:57:49 -07:00 |
|
tangxifan
|
ac6268d9ae
|
[Engine] Bug fix on compilation errors
|
2021-09-29 16:24:36 -07:00 |
|
tangxifan
|
c5ae93f177
|
[Engine] Upgraded fabric generator to support shifter register banks in Quicklogic memory bank
|
2021-09-29 16:17:40 -07:00 |
|
tangxifan
|
5da8f1db73
|
[Engine] Upgrading fabric generator to connect nets between top module and BL/WL shift register modules
|
2021-09-28 23:27:47 -07:00 |
|
tangxifan
|
7723e00e6c
|
[Engine] Adding the function that builds a shift register module for BL/WLs
|
2021-09-28 22:49:24 -07:00 |
|
tangxifan
|
834bdd2b07
|
[Engine] Updating fabric generator to support BL/WL shift registers. Still WIP
|
2021-09-28 17:29:03 -07:00 |
|
tangxifan
|
afd03d7eb7
|
[Engine] Add more check codes for the CCFF circuit model used by BL/WL shift registers
|
2021-09-28 15:56:07 -07:00 |
|
tangxifan
|
0d72e115ac
|
[Engine] Bug fix for the undriven WLR nets in top-level modules
|
2021-09-28 11:53:38 -07:00 |
|
tangxifan
|
33e9b27cb8
|
[Engine] Fixed a critical bug when building final bitstream, which may cause loss when merging BLs
|
2021-09-25 20:22:27 -07:00 |
|
tangxifan
|
29c351f5a4
|
[Engine] Bug fix in estimating the configuration cycles for Verilog testbench generator
|
2021-09-25 19:34:21 -07:00 |
|
tangxifan
|
e06ac11630
|
[Engine] Bug fix
|
2021-09-25 19:21:16 -07:00 |
|
tangxifan
|
3cf31f1565
|
[Engine] Fixed bugs
|
2021-09-25 18:22:55 -07:00 |
|
tangxifan
|
a56d1f4fdb
|
[FPGA-Verilog] Upgraded testbench generator to support memory bank using flatten BL/WLs
|
2021-09-25 17:49:15 -07:00 |
|
tangxifan
|
386812777c
|
[FPGA-Bitstream] Upgraded bitstream writer to support flatten BL/WLs
|
2021-09-25 12:49:32 -07:00 |
|
tangxifan
|
1a2a2a6e63
|
[FPGA-Bitstream] Relax fabric bitstream address check
|
2021-09-25 12:03:33 -07:00 |
|
tangxifan
|
8b72447dad
|
[FPA-Bistream] Updating fabric bitstream writer to organize bitstream for flatten BL/WLs
|
2021-09-24 18:07:07 -07:00 |
|
tangxifan
|
a49e3fe57a
|
[FPGA-bitstream] Upgraded bitstream generator to support flatten BL/WLs for QL memory bank
|
2021-09-24 16:30:18 -07:00 |
|
tangxifan
|
2de4a460a8
|
[Engine] Rework the function that counts the number of configurable children for fabric key writer and bitstream generator
|
2021-09-24 15:15:32 -07:00 |
|
tangxifan
|
74ffc8578f
|
[Engine] Upgraded fabric generator to support flatten BL/WL bus for memory banks
|
2021-09-24 15:05:25 -07:00 |
|
tangxifan
|
be4c850d2d
|
[Engine] Split the function to add BL/WL configuration bus connections for support flatten BL/WLs
|
2021-09-24 12:03:35 -07:00 |
|
tangxifan
|
18257b3fa1
|
[Engine] Update BL/WL port addition for the top-level module in fabric generator
|
2021-09-24 11:07:58 -07:00 |
|
tangxifan
|
7e27c0caf3
|
[Engine] Upgrading top-module fabric generation to support QL memory bank with flatten BL/WLs
|
2021-09-23 16:16:39 -07:00 |
|
tangxifan
|
8c281a22b0
|
[Engine] Add check codes to validate circuit models for BL/WL protocols
|
2021-09-23 14:39:16 -07:00 |
|
tangxifan
|
962acda810
|
[Engine] Bug fix in fabric key generation when computing configurable children
|
2021-09-22 11:09:46 -07:00 |
|
tangxifan
|
ad432e4d95
|
[Engine] Bug fix in finding the start index of BL/WL for each column/row;
|
2021-09-22 10:20:40 -07:00 |
|
tangxifan
|
b0a471bdc9
|
[Engine] Bug fix in outputting fabric key with coordinates
|
2021-09-21 15:55:11 -07:00 |
|
tangxifan
|
7688c0570f
|
[Engine] Support coordinate definition in fabric key file format; Now QL memory bank can accept fabric key
|
2021-09-21 15:08:08 -07:00 |
|
tangxifan
|
c84c0d4a3f
|
[FPGA-Verilog] Upgrade fpga-verilog to support decoders with WLR
|
2021-09-20 17:07:26 -07:00 |
|
tangxifan
|
36a4da863c
|
[Engine] Support WLR port in OpenFPGA architecture file and fabric generator
|
2021-09-20 16:05:36 -07:00 |
|
tangxifan
|
2e45a6143b
|
[Engine] Fix a critical bug which causes flatten memory tests failed
|
2021-09-15 15:11:58 -07:00 |
|
tangxifan
|
f2aa31ddb1
|
[FPGA-Bitstream] Fix the bug which causes bitstream wrong for QL memory bank
|
2021-09-15 13:45:30 -07:00 |
|
tangxifan
|
061952b7fa
|
[Engine] Bug fix in computing local WLs for GRID/CB/SB
|
2021-09-15 11:51:00 -07:00 |
|
tangxifan
|
26b1e48723
|
[Engine] Merge BL/WLs in the Grid/CB/SB modules
|
2021-09-15 11:27:55 -07:00 |
|
tangxifan
|
4af6413c97
|
[Engine] Fixed a critical bug on WL arrangement; Previously we always consider squart of a local tile. Now we apply global optimization where the number of WLs are determined by the max. number of BLs per column
|
2021-09-10 17:03:44 -07:00 |
|
tangxifan
|
ba1e277dc9
|
[Engine] Fix a few bugs in the BL/WL arrangement and now bitstream generator is working fine
|
2021-09-10 15:05:46 -07:00 |
|
tangxifan
|
35c7b09888
|
[Engine] Bug fix for mistakes in calculating number of BLs/WLs for QL memory bank
|
2021-09-09 15:23:29 -07:00 |
|
tangxifan
|
b787c4e100
|
[Engine] Register QL memory bank as a legal protocol
|
2021-09-09 15:06:51 -07:00 |
|
tangxifan
|
1aac3197eb
|
[FPGA-Verilog] Upgrade testbench generator to support QL memory bank
|
2021-09-05 21:38:00 -07:00 |
|
tangxifan
|
6f09f5f7ad
|
[FPGA-Bitstream] Upgrade bitstream generator to support QL memory bank
|
2021-09-05 21:25:58 -07:00 |
|
tangxifan
|
1085e468e2
|
[Engine] Move most utilized functions for memory bank configuration protocol to a separated source file
|
2021-09-05 20:45:56 -07:00 |
|
tangxifan
|
475ce2c6d9
|
[Engine] Upgrade fabric generator in support QL memory bank connections
|
2021-09-05 17:49:01 -07:00 |