3 Commits

Author	SHA1	Message	Date
tangxifan	a04631305c	remove legacy verilog utils functions	2019-12-04 18:02:26 -07:00
tangxifan	73386dd1a9	refactored the Verilog header generation	2019-12-04 17:55:05 -07:00
tangxifan	95ea513339	move refactored Verilog routing block generation functions to cpp files	2019-12-04 16:09:27 -07:00