riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
1,772 Commits 70 Branches 8 Tags 105 MiB
Commit Graph

3 Commits

Author SHA1 Message Date
tangxifan 73386dd1a9 refactored the Verilog header generation 2019-12-04 17:55:05 -07:00
tangxifan 9cf8683acd add module generation for memories 2019-10-22 15:31:08 -06:00
tangxifan 0399319212 refactored LUT Verilog generation 2019-09-11 17:04:43 -06:00