3 Commits

Author	SHA1	Message	Date
Lalit Sharma	2484721a45	Updating write_verilog_testbench by removing option explicit_port_mapping	2020-12-22 22:17:50 -08:00
tangxifan	fd80cacaa3	[Flow] Add example script for behaviorial verilog generation	2020-11-22 21:14:10 -07:00
tangxifan	655da9f3d0	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00