tangxifan
|
722a9bcf63
|
[HDL] Add scan-chain DFF cell with configuration enable signal
|
2021-01-04 14:31:26 -07:00 |
|
tangxifan
|
ff53d2c375
|
[HDL] Add new Scan-chain DFF cell
|
2020-11-30 17:54:10 -07:00 |
|
tangxifan
|
ad703ad85b
|
[HDL] Add new gpio cell with protection circuitry
|
2020-11-30 17:52:39 -07:00 |
|
tangxifan
|
5eb04e6fff
|
[HDL] Correct bugs in MUX2 standard cell where iverilog has problems in deposit initial signals
|
2020-11-22 20:53:32 -07:00 |
|
tangxifan
|
1a79a55646
|
[HDL] Add DFF cell with reset but only 1 output
|
2020-11-06 11:19:19 -07:00 |
|
tangxifan
|
7d46b35296
|
[HDL] Add single-output DFF HDL
|
2020-11-06 10:18:37 -07:00 |
|
tangxifan
|
c074e88dcd
|
[HDL] Add embedded I/O HDL for Caravel SoC interface
|
2020-11-04 17:09:59 -07:00 |
|
tangxifan
|
c036c87d6d
|
[HDL] Bug fix in the GP output pad
|
2020-11-02 18:37:53 -07:00 |
|
tangxifan
|
7e9e0ec9d4
|
[HDL] Bug fix in I/O HDL code
|
2020-11-02 15:15:45 -07:00 |
|
tangxifan
|
2f237a6240
|
[HDL] Add HDL codes for embedded I/Os
|
2020-11-02 14:01:27 -07:00 |
|
tangxifan
|
019208ec0f
|
[Architecture] Reorganize the cell netlists and update architecture files accordingly
|
2020-09-25 11:55:28 -06:00 |