0a3c746fb1
now split CB module bus ports into lower/upper parts
2020-07-01 14:37:13 -06:00
cb2baed257
bug fix in simulation ini GPIO width
2020-07-01 13:39:12 -06:00
b74dde919d
add additional information in the simulation ini file for UVM
2020-07-01 13:07:39 -06:00
e688ca1388
update fabric bitstream writer to support various configuration protocols
2020-07-01 11:54:28 -06:00
73e75bf456
add readme for OpenFPGA architecture naming
2020-07-01 10:27:21 -06:00
20cf4acda0
add readme for architecture file naming
2020-07-01 09:54:13 -06:00
1015880d0e
use easy-to-access net look up in switch block module builder
2020-06-30 18:15:41 -06:00
05187f8aa4
use typedef to short the module pin information
2020-06-30 18:07:22 -06:00
2e7684b746
adapt bus ports in connection block module builder
2020-06-30 17:50:53 -06:00
2ef083c49d
adapt SB module builder to use bus ports
2020-06-30 16:02:40 -06:00
f023652ac4
keep optimizing memory footprint of module manager by using net terminal storage
2020-06-30 14:18:05 -06:00
f49cabeeda
optimize memory efficiency for module net id storage
2020-06-30 11:33:06 -06:00
23bcad0678
use more robust net builder in inter tile connections
2020-06-30 10:49:17 -06:00
025d4a3599
use efficient net builder in top module connection builder
2020-06-29 23:28:26 -06:00
e7d5736269
add profile time to top module builder for better spot on runtime/memory overhead sources
2020-06-29 23:17:03 -06:00
57e6c84252
add reserve net sources and sinks to module manager
2020-06-29 22:49:11 -06:00
66746f69da
optimizing memory efficiency by reserving nets in module manager
2020-06-29 21:27:43 -06:00
e9937954f2
optimizing the constant writing in Verilog for single bits
2020-06-29 12:29:25 -06:00
933801cfa7
update documentation about alias support in fabric key
2020-06-27 15:04:04 -06:00
b2fb5f760c
update sample key
2020-06-27 15:01:12 -06:00
9d32a5b81f
add alias name support for fabric key
2020-06-27 14:59:53 -06:00
ebf5636e7b
add verbose output to edge sorting for GSBs
2020-06-26 17:10:51 -06:00
b36da17a08
bug fix for directory creation when the input is an empty string
2020-06-25 10:34:34 -06:00
e2d3ac78ec
skip empty lines in OpenFPGA shell
2020-06-25 10:18:05 -06:00
db5397fa75
update tutorial about architecture to synchronize with latest file organization
2020-06-24 10:51:26 -06:00
161d1474c1
keep tutorial updated to the latest regression test organization
2020-06-24 10:36:08 -06:00
aded675633
rename files in fpga bitstream library to be consistent with conventions
2020-06-21 13:06:39 -06:00
2f33c35a4f
add example XML file for bitstream
2020-06-20 19:05:44 -06:00
3bcdd0e1d4
clean up writer format for bitstream
2020-06-20 19:01:33 -06:00
8b8d92d186
update documentation for new bitstream file format
2020-06-20 18:59:45 -06:00
d526f08782
deploy bitstream reader in openfpga shell
2020-06-20 18:48:19 -06:00
1e763515b3
bug fix in bitstream parser and writer
2020-06-20 18:39:21 -06:00
675a59ecb8
Move fpga_bitstream to the libopenfpga library and add XML reader
2020-06-20 18:25:17 -06:00
91b072d7c5
documentation update on the bitstream file format to synchronize with the latest codes
2020-06-17 11:56:40 -06:00
5d79a3f69f
critical bug fixed when annotating the routing results.
...
Add previous node check. This is due to that some loops between SB/CBs may exist
when routing congestion is high, which leads to same nets appear in the inputs
of a routing multiplexer. Actually one of them is driven by the other as a downstream node
Using previous node check can identify which one to pick
2020-06-17 11:17:57 -06:00
4f7e8020a8
minor fix on the format of arch bitstream writer
2020-06-17 00:08:28 -06:00
b91c30191a
add input and output net echo in arch bitstream database
2020-06-17 00:04:55 -06:00
19c0b57df6
ignore invalid nets when decoding bitstream
2020-06-16 22:26:36 -06:00
9d0e002532
echo path in architecture bitstream database
2020-06-16 21:29:45 -06:00
3d56cd3060
fine tuning on the script for MCNC benchmarks
2020-06-15 20:09:46 -06:00
e1a1627899
deploy load external key test case to CI
2020-06-12 21:41:21 -06:00
0d81f60fd8
add new options to openfpga task configuration files
2020-06-12 19:48:39 -06:00
559564c333
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
2020-06-12 17:31:14 -06:00
ba38120093
add documentation for fabric key and reorganize command references
2020-06-12 16:15:16 -06:00
41585436c8
Added external_fabric_key_file key
2020-06-12 15:37:12 -06:00
2d35848cfa
add external key test cases
2020-06-12 13:11:21 -06:00
a5055e9d26
add support about loading external fabric key
2020-06-12 13:03:11 -06:00
76b82e348f
deploy fabric key test cases to CI
2020-06-12 11:38:05 -06:00
65b387a589
develop test cases for fabric keys
2020-06-12 11:32:52 -06:00
9dbf536306
add shuffled configurable children support for top module
2020-06-12 11:16:53 -06:00
tangxifan
ganeshgore