riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
3,426 Commits 70 Branches 8 Tags 105 MiB
Commit Graph

3426 Commits

Author SHA1 Message Date
tangxifan 722a9bcf63 [HDL] Add scan-chain DFF cell with configuration enable signal 2021-01-04 14:31:26 -07:00
Ashton Snelgrove cf022c63a1 Fix mismatch in clang 6 names. 2021-01-04 11:31:14 -07:00
tangxifan a9f91513f6
Merge pull request #156 from lnis-uofu/quicklogic_test 
Adding a testcase to run yosys quicklogic flow
 2020-12-24 23:08:40 -07:00
Lalit Sharma 2484721a45 Updating write_verilog_testbench by removing option explicit_port_mapping 2020-12-22 22:17:50 -08:00
Ashton Snelgrove 6f42d0c795 Add missing tcl dependencies 2020-12-22 18:14:09 -07:00
Ashton Snelgrove e280b5b344 Add docker build workflow and fix submodule issues. 2020-12-22 17:37:14 -07:00
Ashton Snelgrove b29fca6bfa Merge remote-tracking branch 'origin/master' into github-action-optimizations 2020-12-22 11:37:39 -07:00
tangxifan 67b9a5a9c0
Merge pull request #163 from lnis-uofu/tangxifan-patch-1 
Dead link patch to fontpage README
 2020-12-21 14:01:45 -07:00
tangxifan 25b0b84133
Broken link patch to fontpage README 2020-12-21 11:33:36 -07:00
Lalit Sharma 2a1c484055 Merge remote-tracking branch 'origin/master' into quicklogic_test 2020-12-20 23:43:02 -08:00
tangxifan 668c531e8e
Merge pull request #162 from lnis-uofu/bump_yosys 
Bumping latest updates to yosys submodule
 2020-12-18 11:31:48 -07:00
Lalit Sharma 6d75108bc4 Bumping latest updates to yosys submodule 2020-12-18 04:02:12 -08:00
Lalit Sharma 3c9e4919b4 Updating variable name in ys to call BLIF output file. 2020-12-18 03:18:46 -08:00
Lalit Sharma 1f994319fd Adding this testcase to CI script. Also adding an option in ys script for synthesis to use openfpga compliant FF 2020-12-16 04:19:56 -08:00
Lalit Sharma 891e2f8aa3 Adding arch xml from SOFA repo. Also updating the script with its file location 2020-12-16 04:14:18 -08:00
Lalit Sharma 3e4732e8b2 Merge remote-tracking branch 'origin/master' into quicklogic_test 
Merging latest updates from master.
 2020-12-16 03:50:51 -08:00
tangxifan 6b15ae6805
Merge pull request #152 from lnis-uofu/replace_yosys 
Replace yosys
 2020-12-15 08:24:39 -07:00
Lalit Sharma 0e7c04878c Merge remote-tracking branch 'origin/master' into replace_yosys 
Merging latest changes from master.
 2020-12-14 20:57:26 -08:00
Lalit Sharma 682f9fa802 Merge remote-tracking branch 'origin/master' into replace_yosys 2020-12-14 20:18:54 -08:00
tangxifan 7f297114b6
Merge pull request #160 from lnis-uofu/dev 
[Git] Add labeler for pull requests
 2020-12-14 15:13:34 -07:00
tangxifan 5a0fbe7705 [Git] Use main version of labeler 2020-12-14 13:40:40 -07:00
tangxifan 1e19039b9a [Git] Use specific path to labeler configuration file 2020-12-14 13:37:28 -07:00
tangxifan 279d259fd7 [Git] Use compatible ubuntu version for labeler 2020-12-14 12:16:45 -07:00
tangxifan abc1b51771 [Git] Add labeler for pull requests 2020-12-14 11:38:17 -07:00
tangxifan e51c90db46
Merge pull request #159 from lnis-uofu/dev 
Add default pull request template to the right position that Github requires
 2020-12-14 11:26:05 -07:00
tangxifan 4204e98ffa [Git] Add default pull request template to the right position that Github prefers 2020-12-14 10:29:53 -07:00
tangxifan 5bda464ca0
Merge pull request #158 from lnis-uofu/dev 
Bug fix on the incompatible sphinx bibtex version
 2020-12-14 10:26:54 -07:00
Lalit Sharma 2b6dbb7cd6 Adding target compile in Makefile that just compiles without updating submodules 2020-12-14 09:25:50 -08:00
tangxifan 024bc17b84 [Doc] Bug fix on the incompatible sphinx bibtex version. Constrain to the right version. 2020-12-14 09:37:45 -07:00
Lalit Sharma 3ccd6b80dd Updating compile.rst file with updated compilation steps 2020-12-13 21:04:10 -08:00
Lalit Sharma 3a82bae1ac Updating compilation steps 2020-12-11 03:51:23 -08:00
Lalit Sharma b621c4f694 Removing yosys-symbiflow-plugins compilation from CMakefile 2020-12-10 21:44:57 -08:00
Lalit Sharma 6991848f97 Removing yosys-symbiflow-plugins submodule and will be added separately later via another PR 2020-12-10 21:06:08 -08:00
tangxifan 780be05079
Merge pull request #154 from lnis-uofu/dev 
Add pull request template
 2020-12-10 16:39:59 -07:00
Ashton Snelgrove d77aa19ae1 Run tests in parallel 2020-12-10 15:49:02 -07:00
Ashton Snelgrove faec0ea782 Github action optimizations 2020-12-10 14:35:19 -07:00
Lalit Sharma 0ee3efb306 Adding a testcase to run yosys quicklogic flow 2020-12-10 02:41:43 -08:00
Lalit Sharma f805a62f96 Updating yosys branch to quicklogic-rebased 2020-12-09 23:36:13 -08:00
Lalit Sharma 3b302dd538 Updating yosys URL to pick from QuickLogic-Corp repo, this is done till this repo is merged to mainstream repo 2020-12-09 22:25:51 -08:00
Lalit Sharma 760b8bd7ad Adding tcl8.6-dev package as CI dependency 2020-12-08 21:14:48 -08:00
Lalit Sharma 07dfd35e12 Adding yosys-symbiflow-plugins as submodule and adding tcllib as dependency in CI 2020-12-08 20:35:57 -08:00
tangxifan c278bb0a5f [Git] Format fix on pull request template 2020-12-08 17:29:30 -07:00
tangxifan e20c8d578e [Git] Format pull request template and add more OpenFPGA-related topics 2020-12-08 17:27:48 -07:00
tangxifan 6383946ae6 [Git] Add pull request template 2020-12-08 17:16:50 -07:00
tangxifan 6b50bbf986
Merge pull request #134 from lnis-uofu/ganesh_dev 
Support Delay Customization in OpenFPGA Task Configuration File
 2020-12-08 15:32:48 -07:00
Lalit Sharma 8a2681f99f Re-setting option YOSYS_ENABLE_TCL to ON, as yosys compilation depends on tcl 2020-12-08 09:21:25 -08:00
Lalit Sharma 3a7bc77871 Correcting the syntax for CI run 2020-12-08 09:14:05 -08:00
Lalit Sharma d7ec481e9e Adding updates to checkout submodules 2020-12-08 08:52:35 -08:00
Lalit Sharma ed9535693c Updating CMakeList.txt to compile yosys 2020-12-08 01:29:36 -08:00
Lalit Sharma 460bf9d3bd Adding yosys sub-module instead of yosys folder 2020-12-07 23:54:18 -08:00