e7ab7a61f1
[doc] update to use tile name and index when defining clock taps
2024-08-09 18:09:12 -07:00
85c9bdc6f9
[doc] add new format
2024-08-06 17:28:03 -07:00
c11a2c7381
[doc] format to resolve latexpdf build errors; now local build passes
2024-08-03 15:03:14 -07:00
22d7df5ffb
Update doc
2024-07-28 02:40:24 -07:00
cbe9a46f95
Format and update doc
2024-07-28 00:02:20 -07:00
0ff0c3445e
Update doc
2024-07-26 13:43:31 -07:00
0c99fcf6f4
[doc] format
2024-07-10 15:07:57 -07:00
a390aad0b8
[doc] add new syntax
2024-07-10 15:07:16 -07:00
f42884304a
[doc] update clock network details
2024-07-09 11:40:41 -07:00
bf484dbc70
[doc] add perimeter cb examples on prog clk network
2024-07-08 21:25:12 -07:00
229adebe07
[doc] new option to write_fabric_verilog
2024-07-08 21:06:12 -07:00
8a5c33b1d6
[doc] new option for perimeter cb
2024-07-08 19:01:16 -07:00
4da5150a26
[doc] update for bottom-left tile organization
2024-07-07 14:20:26 -07:00
91f8bb5841
[doc] update figures for ecb
2024-07-07 13:40:01 -07:00
e3a258a5ab
[doc] typo
2024-07-02 19:31:45 -07:00
ec7ca1add1
[doc] add example to example clock network
2024-07-01 21:41:33 -07:00
18e2b994ac
[doc] update syntax on clock network file
2024-06-30 22:56:31 -07:00
1094af9f73
[doc] add new options to route clock graph
2024-06-28 12:38:40 -07:00
3fb891094b
[doc] add new syntax
2024-06-27 11:02:37 -07:00
ec1ad94d4a
[doc] add syntax about internal drivers
2024-06-25 13:06:47 -07:00
253e3e0cba
[doc] add new syntax for clock network
2024-06-23 17:43:38 -07:00
b491ba03b7
[doc] typo
2024-05-29 10:33:39 -07:00
391b768b3a
[doc] syntax
2024-05-21 11:14:12 -07:00
4c6b923b74
[doc] add a figure about ecb
2024-05-21 11:03:58 -07:00
5775187072
[doc] enhance connection block details and restrictions
2024-05-21 10:55:13 -07:00
be1d7517c9
[doc] rework out-of-date syntax
2024-05-17 19:25:35 -07:00
79c5c0a26a
[doc] add more comments
2024-05-02 22:38:39 -07:00
f965595d17
[doc] add example file and file format details
2024-05-02 22:37:07 -07:00
e4998eebe0
[doc] add new options for write_fabric_hierarchy
2024-05-02 22:29:18 -07:00
dd577e37e0
LUTRAM Support ( #1595 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
* LUTRAM Support Phase 1
* Add Test
* Add more protocol checking to enable LUTRAM feature
* Move the config setting under config protocol
* Revert any changes
---------
Co-authored-by: chungshien-chai <chungshien.chai@gmail.com>
2024-04-19 14:46:38 -07:00
dfc2626502
[doc] add hyperlinks
2024-04-11 15:46:52 -07:00
63128cb944
[doc] add new file format and new command as well as related options
2024-04-11 15:44:12 -07:00
f04e255b1f
[doc] add new option ``--dump_waveform``
2024-03-29 10:29:38 -07:00
4365d160ff
Support extracting data that is not affecting fabric bitstream ( #1566 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
2024-03-09 17:38:31 -08:00
073161f523
[doc] add new option
2023-12-12 14:20:51 -08:00
2879bf2e6e
[doc] add new option
2023-12-08 13:56:46 -08:00
37352cf25c
Update fpga_bitstream_commands.rst with ref check marker.
2023-12-04 11:54:49 -08:00
04f2bdf5e3
Update repack_design_constraints.rst
...
Add subsections for each command.
2023-12-04 11:49:32 -08:00
26b2eb0970
add priority info to fpga_bitstream_commands.rst
2023-12-04 14:37:46 +08:00
9ffdcbff05
Update repack_design_constraints.rst
2023-12-04 14:05:03 +08:00
80102e1d8a
Update repack_design_constraints.rst
...
add explaination for new command: ignore_net
2023-12-01 15:52:29 +08:00
b79703fc8b
[doc] comment on new options
2023-11-14 10:10:41 -08:00
e9673916b2
[doc] add figures for new options in tileable rr graph
2023-11-14 09:56:57 -08:00
442dc9ddec
[doc] format
2023-11-02 21:27:12 -07:00
16f4e2938f
[doc] add new comand
2023-11-02 21:22:37 -07:00
2e6723d2a9
[doc] update for new options that are added to ``write_fabric_bitstream``
2023-10-06 19:32:42 -07:00
517be141ba
[doc] format
2023-09-26 18:37:49 -07:00
b56609d210
[doc] more details
2023-09-26 15:11:26 -07:00
262e47a922
[doc] update
2023-09-25 22:34:10 -07:00
c3443a288c
[doc] update doc for module rename assistant
2023-09-22 19:36:01 -07:00
tangxifan
chungshien-chai
chungshien
Yitian4Debug
Jingrong Lin