3 Commits

Author	SHA1	Message	Date
tangxifan	73386dd1a9	refactored the Verilog header generation	2019-12-04 17:55:05 -07:00
tangxifan	e64cfc5852	start refactoring memory decoders	2019-09-13 20:58:55 -06:00
tangxifan	62853c092f	refactoring local encoders. Ready to plug in	2019-09-10 15:16:29 -06:00