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OpenFPGA
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3 Commits

Author SHA1 Message Date
Lalit Sharma d842026672 Disabling verilog testbench generation for quicklogic tests 2021-02-21 21:58:23 -08:00
Tarachand Pagarani 426b6449d8 change the test to turn off power analysis 2021-02-15 02:45:38 -08:00
Lalit Sharma 2484721a45 Updating write_verilog_testbench by removing option explicit_port_mapping 2020-12-22 22:17:50 -08:00