tangxifan
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cb07848475
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[Script] Remove verilog and SDC generation from vtr benchmark openfpga script; Focus on bitstream generation
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2021-03-20 18:11:54 -06:00 |
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tangxifan
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deee7ba366
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[Script] Add example script to run vtr benchmarks
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2021-03-17 15:10:56 -06:00 |
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tangxifan
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e34380a654
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Merge branch 'master' into default_net_type
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2021-03-01 08:38:58 -07:00 |
Lalit Sharma
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ea4aee8cb2
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For time-being yosys script running in no_adder mode.
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2021-02-28 22:07:23 -08:00 |
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tangxifan
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b4b6ada06f
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[Script] Correct bugs in example scripts using default_net_type
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2021-02-28 16:31:44 -07:00 |
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tangxifan
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8cc2c7d924
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[Script] Bug fix for default net type example script
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2021-02-28 12:35:44 -07:00 |
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tangxifan
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0723b79bce
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[Script] Add example script for verilog default net type
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2021-02-28 12:29:56 -07:00 |
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tangxifan
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ae05871b1f
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[Script] Remove default net type from an example script; Limit it to some test cases
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2021-02-28 12:19:14 -07:00 |
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tangxifan
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d7eb159726
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[Script] Add default net type option to example openfpga shell scripts
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2021-02-28 12:08:30 -07:00 |
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tangxifan
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744d87cb4e
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[Script] Now use implicit port mapping for Verilog testbenches to avoid renaming issues
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2021-02-26 09:34:52 -07:00 |
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tangxifan
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c7a9a4e896
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[Flow] Add new script to run bitstream generation for multi-clock fix-size FPGAs
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2021-02-22 15:01:50 -07:00 |
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tangxifan
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2bb588dacf
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[Flow] Add a new script for generating bitstream for multi-clock architectures
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2021-02-22 11:31:24 -07:00 |
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tangxifan
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d6a02a985e
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Merge pull request #248 from lnis-uofu/add_quicklogic_tests
Disabling verilog testbench generation for quicklogic tests
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2021-02-22 09:02:29 -07:00 |
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Lalit Sharma
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d842026672
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Disabling verilog testbench generation for quicklogic tests
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2021-02-21 21:58:23 -08:00 |
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tangxifan
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d85d6e964e
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Merge pull request #227 from watcag/master
Standard-cell flow
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2021-02-17 10:11:34 -07:00 |
Tarachand Pagarani
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426b6449d8
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change the test to turn off power analysis
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2021-02-15 02:45:38 -08:00 |
Nachiket Kapre
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4c7f4bd82f
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ahoy nice
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2021-02-09 17:38:19 -05:00 |
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Nachiket Kapre
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71c76df063
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default to ns for time unit -- synopsys dc whines
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2021-02-09 17:08:38 -05:00 |
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Nachiket Kapre
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6bb2e29f17
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default to ns for time unit -- synopsys dc whines
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2021-02-09 17:04:52 -05:00 |
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tangxifan
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8853370c60
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[Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file
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2021-02-04 20:20:10 -07:00 |
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tangxifan
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d3397f6936
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[Script] Remove activity from bitstream setting example script
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2021-02-02 09:25:36 -07:00 |
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tangxifan
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7f14dfbe87
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[Script] Add example script to use bitstream setting
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2021-02-02 09:18:08 -07:00 |
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tangxifan
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8b74947737
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[Script] Now multi-clock openfpga shell script no longer needs activity file
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2021-01-29 11:40:33 -07:00 |
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tangxifan
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3fdd5ae8b3
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[Script] Use pin constraints in template script
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2021-01-19 17:42:25 -07:00 |
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tangxifan
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12e0efd03e
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[Script] Add an example openfpga script to use repack design constraints
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2021-01-17 10:33:56 -07:00 |
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tangxifan
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c5a2027f36
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[Flow] Use implicit port mapping to avoid renaming problem between yosys and VPR
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2021-01-13 15:41:48 -07:00 |
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tangxifan
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18d2a8ce19
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[Flow] Add new script for fixed device layout using global tile clock
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2021-01-10 11:08:02 -07:00 |
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Lalit Sharma
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2484721a45
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Updating write_verilog_testbench by removing option explicit_port_mapping
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2020-12-22 22:17:50 -08:00 |
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tangxifan
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fd80cacaa3
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[Flow] Add example script for behaviorial verilog generation
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2020-11-22 21:14:10 -07:00 |
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tangxifan
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655da9f3d0
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |