tangxifan
|
7f67794787
|
[arch]add new arch to test
|
2022-10-13 10:54:40 -07:00 |
|
tangxifan
|
088ff1a474
|
[script] fixed a bug
|
2022-09-29 16:27:03 -07:00 |
|
tangxifan
|
a3e7133d63
|
Merge branch 'master' into wire_lut_test
|
2022-09-29 16:02:18 -07:00 |
|
tangxifan
|
ce0fbe1765
|
[test] fixed a few bugs
|
2022-09-29 15:32:31 -07:00 |
|
tangxifan
|
3f8e2ade2e
|
[script] update missing scripts required by pb_pin_fixup test cases
|
2022-09-29 13:39:46 -07:00 |
|
tangxifan
|
49fa783914
|
[script] now suggest to skip pb_pin_fixup step in example scripts for most test cases
|
2022-09-29 10:45:27 -07:00 |
|
tangxifan
|
eaa0b5588a
|
[test] fixed a bug in pin constrain examples
|
2022-09-21 14:10:12 -07:00 |
|
tangxifan
|
baac236ed7
|
[test] fixed a bug in example scripts due to the changes on vpr options
|
2022-09-21 10:52:49 -07:00 |
|
tangxifan
|
d0b018ad6e
|
[script] mismatches in vpr options due to upgrade
|
2022-09-21 09:27:26 -07:00 |
|
tangxifan
|
b630d60b7e
|
[test] update arch bitstream and force a pin placement for the test case where external bistream is fixed
|
2022-09-20 14:14:18 -07:00 |
|
tangxifan
|
37c5056d6a
|
[test] now use a fixed routing channel width for quicklogic tests
|
2022-09-20 12:25:40 -07:00 |
|
tangxifan
|
846ca26311
|
[test] enable block usage information output when running vpr. Otherwise some testcases miss the information for QoR checks
|
2022-09-20 12:08:24 -07:00 |
|
tangxifan
|
63cb8d589d
|
[test] fixed a typo
|
2022-09-19 23:14:15 -07:00 |
|
tangxifan
|
d9bd0a6cf3
|
[test] disable clustering-routing result sync-up when calling vpr in example scripts
|
2022-09-19 20:52:04 -07:00 |
|
tangxifan
|
fca1c82388
|
[test] disable clustering and routing sync when using VPR
|
2022-09-19 20:33:35 -07:00 |
|
tangxifan
|
373566416c
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
|
2022-09-16 16:47:21 -07:00 |
|
tangxifan
|
1c2192a87d
|
[engine] fixed a few bugs
|
2022-09-12 16:50:32 -07:00 |
|
tangxifan
|
0d6e4e3979
|
[test] add a new example for the repack options
|
2022-09-12 16:21:49 -07:00 |
|
tangxifan
|
56619f9a47
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
|
2022-09-07 15:04:05 -07:00 |
|
tangxifan
|
477e2119d7
|
[test] remove abs paths in golden outputs without time stamps
|
2022-09-06 15:24:43 -07:00 |
|
tangxifan
|
561d0a6545
|
[test] add more test case to track golden outputs for representative fpga sizes
|
2022-09-06 14:04:23 -07:00 |
|
tangxifan
|
c691eb0e95
|
Merge branch 'master' into vtr_upgrade
|
2022-09-01 15:54:14 -07:00 |
|
tangxifan
|
51dc082bd4
|
[test] force a fixed routing chan W for no time stamp test case
|
2022-09-01 15:02:40 -07:00 |
|
tangxifan
|
d86eb04c5d
|
[test] now no timestamp test case covers gsb files
|
2022-09-01 14:03:51 -07:00 |
|
tangxifan
|
dbacee8a0a
|
[script] turn off equivalent for soft adder architecture as we do not expect any routing optimization
|
2022-08-27 20:25:50 -07:00 |
|
tangxifan
|
ef3381a1b2
|
[script] also turn off pb_pin_fixup in vpr for quicklogic tests
|
2022-08-27 20:07:49 -07:00 |
|
tangxifan
|
b9fade4c76
|
[script] turn off the pb_pin_fix_up in vpr run for mcnc and vtr benchmarks
|
2022-08-27 20:04:29 -07:00 |
|
tangxifan
|
e9d6e7e38a
|
[engine] update vtr and enable more debugging info
|
2022-08-27 19:12:43 -07:00 |
|
tangxifan
|
ec31e124b7
|
[test] reworked test case on pcf2place
|
2022-07-28 11:51:56 -07:00 |
|
tangxifan
|
23f98d6a3b
|
[engine] fixed a few bugs
|
2022-07-26 13:55:29 -07:00 |
|
tangxifan
|
353de4546f
|
[test] add 'write_fabric_io_info' command to test cases
|
2022-07-26 13:48:54 -07:00 |
taoli4rs
|
3762a3aae4
|
Code clean up based on review.
|
2022-07-20 14:34:44 -07:00 |
|
taoli4rs
|
cfc0d08060
|
Add constrain_pin_location command in openfpga; add full flow test.
|
2022-07-20 11:51:00 -07:00 |
|
tangxifan
|
4b9431b132
|
[test] avoid XML bitstream output when can go beyond github runners' disk space
|
2022-05-25 18:45:26 +08:00 |
Ganesh Gore
|
e845b62322
|
Update regession tasks
|
2022-05-05 01:46:19 -06:00 |
|
tangxifan
|
5beefda3bd
|
[Test] Add a new test case to validate the fix_pins option
|
2022-04-13 15:55:21 +08:00 |
|
tangxifan
|
576b9c2d8f
|
[Script] Disable SDC writer in multiclock examples
|
2022-03-20 11:05:29 +08:00 |
|
tangxifan
|
c897a64ad5
|
[Script] Add a new example script to test full testbenches using bus group features
|
2022-02-18 15:37:42 -08:00 |
|
tangxifan
|
a4d5172b7c
|
[Test] Fixed bugs that causes VPR failed
|
2022-02-18 12:31:29 -08:00 |
|
tangxifan
|
73e6ee964d
|
[Script] Add a new example script showing how to use bus group features
|
2022-02-18 12:25:34 -08:00 |
|
tangxifan
|
074811a612
|
[Script] Now counter benchmarks should pass on the implicit verilog test case
|
2022-02-15 16:47:14 -08:00 |
|
tangxifan
|
1370be0817
|
[Script] Fixing bugs
|
2022-02-15 16:44:51 -08:00 |
|
tangxifan
|
8be0868a3b
|
[Test] Update test case which uses counter benchmarks: adding pin constraints
|
2022-02-15 16:29:06 -08:00 |
|
tangxifan
|
d0fe8d96fa
|
[Test] Update template scripts and assoicated test cases by offering more options
|
2022-02-14 16:03:48 -08:00 |
|
tangxifan
|
2fb1df11bb
|
[Script] Add a new example script
|
2022-02-14 15:54:07 -08:00 |
|
tangxifan
|
1d3c9ff192
|
[Script] Adapt python scripts to support include directory
|
2022-02-01 13:55:25 -08:00 |
|
tangxifan
|
35c7968c98
|
[Script] Add a new example openfpga shell script
|
2022-02-01 13:40:22 -08:00 |
|
tangxifan
|
09ef516de8
|
[Script] Tune OpenFPGA shell script to enable testing on relative paths
|
2022-01-31 14:23:13 -08:00 |
|
tangxifan
|
da8fc0f5d4
|
[Test] Add a new test case to validate ``--use_relative_path``
|
2022-01-31 13:02:19 -08:00 |
|
tangxifan
|
e59ea91ad6
|
[Script] Fixed a bug which causes errors
|
2022-01-26 11:49:32 -08:00 |
|
tangxifan
|
f8ef3df560
|
[Test] Now use 4x4 fabric in testing write_rr_gsb commands
|
2022-01-26 11:41:48 -08:00 |
|
tangxifan
|
5db049522d
|
[Script] Add an example script about write GSB
|
2022-01-26 11:22:23 -08:00 |
|
tangxifan
|
fedb1bd2e3
|
[Test] Add new testcases to validate correctness of the testbenches/Verilog netlists without time stamp
|
2022-01-25 16:41:36 -08:00 |
|
tangxifan
|
e4cfa2222f
|
[Script] Add an example script to test option ``--no_time_stamp``
|
2022-01-25 16:16:39 -08:00 |
|
tangxifan
|
ff264c00a2
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
|
2021-10-31 11:51:34 -07:00 |
|
tangxifan
|
335347a74f
|
[Test] Bug fix
|
2021-10-30 15:48:25 -07:00 |
|
tangxifan
|
40d11a45d9
|
[Test] Disable ACE2 in implicit verilog test cases due to Yosys upgrade
|
2021-10-30 14:49:56 -07:00 |
|
tangxifan
|
16de60e943
|
[Test] Turn off ACE2 run in bitstream generation only flows
|
2021-10-30 12:31:14 -07:00 |
|
tangxifan
|
4add9781d5
|
[Script] Add a new openfpga shell script for don't care bits outputting
|
2021-10-05 19:13:50 -07:00 |
|
tangxifan
|
f32ffb6d61
|
[Test] Bug fix
|
2021-06-29 18:51:28 -06:00 |
|
tangxifan
|
56b0428eba
|
[Misc] Bug fix
|
2021-06-29 18:48:19 -06:00 |
|
tangxifan
|
c6089385b0
|
[Misc] Bug fix
|
2021-06-29 18:34:41 -06:00 |
|
tangxifan
|
5f5a03f17f
|
[Misc] Bug fix on test cases that were generating both full testbench and preconfigured testbenches
|
2021-06-29 18:28:38 -06:00 |
|
tangxifan
|
4fb34642ca
|
[Script] Add a new example script for global tile clock running full testbench
|
2021-06-29 17:53:56 -06:00 |
|
tangxifan
|
9655bc35cb
|
[Script] Bug fix due to the full testbench generation changes
|
2021-06-29 17:04:19 -06:00 |
|
tangxifan
|
20faf82e64
|
[Script] Rename example script
|
2021-06-29 16:02:35 -06:00 |
|
tangxifan
|
01391fd81e
|
[Script] Added example scripts that use OpenFPGA to generate testbenches without self checking features
|
2021-06-29 15:56:33 -06:00 |
|
tangxifan
|
4a623bec79
|
[Script] Add example openfpga shell script to generate preconfigured fabric wrapper
|
2021-06-27 19:55:40 -06:00 |
|
tangxifan
|
fae5e1dfdf
|
[Script] Upgrade openfpga shell script with the new option '--embed_bitstream'
|
2021-06-25 15:16:37 -06:00 |
|
tangxifan
|
b2c30e3103
|
[Test] Bug fix in mcnc openfpga shell script
|
2021-06-22 16:40:24 -06:00 |
|
tangxifan
|
96cb3081ab
|
Update fix_device_route_chan_width_example_script.openfpga
|
2021-06-18 09:51:16 -06:00 |
|
tangxifan
|
d40cf98c48
|
[Test] Update test cases by using default net type in testbench generator
|
2021-06-14 11:47:28 -06:00 |
|
tangxifan
|
d545069aac
|
[Script] Bug fix
|
2021-06-09 14:50:37 -06:00 |
|
tangxifan
|
4e3f589810
|
[Script] Patch openfpga shell script to use the new option '--support_icarus_simulator' for 'write_preconfigured_testbench'
|
2021-06-09 13:53:28 -06:00 |
|
tangxifan
|
f9404dc97d
|
[Script] Patch openfpga shell script due to missing a mandatory option in 'write_full_testbench'
|
2021-06-09 11:55:25 -06:00 |
|
tangxifan
|
9adf94bfd3
|
[Script] Update all the openshell scripts to deprecate 'write_verilog_testbench'
|
2021-06-09 11:18:52 -06:00 |
|
tangxifan
|
be26c06673
|
[Script] Update an example script to use 'write_preconfigured_fabric_wrapper' and 'write_preconfigured_testbench' in place of 'write_verilog_testbench'
|
2021-06-09 10:41:22 -06:00 |
|
tangxifan
|
e9fa44cc25
|
[Tool] Add fast configuration to the write bitstream command in example shell script
|
2021-06-04 16:24:56 -06:00 |
|
tangxifan
|
f5e90c9467
|
[Script] Update openfpga shell script with fast configuration option
|
2021-06-04 11:28:10 -06:00 |
|
tangxifan
|
8fc90637e0
|
[Script] Update write_full_testbench example script to support custom device layout in VPR
|
2021-06-03 17:08:08 -06:00 |
|
tangxifan
|
51ca62a464
|
[Script] Add example script for write_full_testbench command
|
2021-06-03 15:48:59 -06:00 |
|
tangxifan
|
7dc7c1b4f5
|
[Script] Add example openfpga shell script showing how to use 'report_bitstream_distribution' command
|
2021-05-07 12:05:47 -06:00 |
|
tangxifan
|
f9fd444b86
|
[Script] Add an write I/O mapping example script for openfpga shell
|
2021-04-27 14:40:26 -06:00 |
|
tangxifan
|
09cc7f0007
|
[Script] Enable constant net routing for heterogeneous FPGAs
|
2021-04-23 20:44:36 -06:00 |
|
tangxifan
|
cbb7d41b6e
|
[Script] Enable constant net routing for VTR benchmarks
|
2021-04-23 14:15:13 -06:00 |
|
tangxifan
|
a16896054d
|
[Script] Enable constant net routing for iwls benchmarks
|
2021-04-22 19:16:32 -06:00 |
|
tangxifan
|
64163edbe6
|
[Script] Add a custom script to run OpenFPGA in a fixed device size using global tile clock and bitstream setting
|
2021-04-19 16:15:25 -06:00 |
|
tangxifan
|
7018073e28
|
[Script] Update openfpga shell script w/o ace usage to adapt pin constraint files
|
2021-04-17 15:04:51 -06:00 |
|
tangxifan
|
c020333512
|
Merge branch 'master' into dff_techmap
|
2021-04-16 20:54:28 -06:00 |
|
tangxifan
|
2666726f36
|
[Script] Remove clock routing from example openfpga shell script without ace
|
2021-04-16 20:46:49 -06:00 |
|
tangxifan
|
23d08757cf
|
[Script] Add example script without using ACE2
|
2021-04-16 20:20:10 -06:00 |
|
tangxifan
|
43bf016576
|
[Script] Add example openfpga shell script for iwls benchmark
|
2021-04-16 16:09:47 -06:00 |
|
tangxifan
|
b469705819
|
Merge branch 'master' into fpga_sdc_test
|
2021-04-11 21:14:46 -06:00 |
|
tangxifan
|
07f6066c11
|
[Script] Update timing unit in SDC example script
|
2021-04-11 20:24:18 -06:00 |
|
tangxifan
|
94c4c817eb
|
[Test] Expand sdc time unit test to sweep all the available units
|
2021-04-11 20:14:09 -06:00 |
|
tangxifan
|
a4893e27cf
|
[Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification
|
2021-04-11 17:26:27 -06:00 |
|
tangxifan
|
44d97ead86
|
Merge branch 'master' into hetergeneous_arch
|
2021-03-23 17:05:03 -06:00 |
|
tangxifan
|
145a80de43
|
[Script] Add an openfpga shell script for heterogeneous fpga verification
|
2021-03-23 15:35:34 -06:00 |
|
tangxifan
|
d050f1b746
|
[Script] Enable fast bitstream generation for VTR benchmarks
|
2021-03-22 12:54:36 -06:00 |
|
tangxifan
|
eca2a35612
|
[Script] Add route chan width option to vtr openfpga script
|
2021-03-20 22:00:09 -06:00 |