tangxifan
|
9832722056
|
[test] now add QuickLogic memory bank to fpga bitstream regression tests
|
2022-05-25 11:42:32 +08:00 |
|
tangxifan
|
86347a9d49
|
[test] move generate_bitstream to another directory. Ready to test generate bitstream across different configuration protocols
|
2022-05-25 11:19:49 +08:00 |
|
tangxifan
|
7d694acf32
|
[test] debugging basic reg test paths
|
2022-05-23 11:21:36 +08:00 |
|
tangxifan
|
b41cbad5d3
|
[test] force to run git diff under root directory
|
2022-05-23 10:32:43 +08:00 |
|
tangxifan
|
488a934097
|
[test] give abs path for git diff in basic regression tests
|
2022-05-23 09:12:33 +08:00 |
|
tangxifan
|
0dc7caf3b7
|
[test] now regression test script supports remove all run dir through command-line options
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2022-05-22 13:15:39 +08:00 |
|
tangxifan
|
751d87b8e3
|
[test] fix a bug in detect changes in golden netlists
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2022-05-22 13:06:47 +08:00 |
|
tangxifan
|
d7e854eae7
|
[test] deploy new test to ci
|
2022-05-09 17:23:57 +08:00 |
Ganesh Gore
|
522982c9ba
|
Adde vtr_benchmarks_template for demo
|
2022-05-06 22:40:36 -06:00 |
|
Ganesh Gore
|
1e243650b9
|
Added option to copy example projects
|
2022-05-03 14:06:16 -06:00 |
|
Ganesh Gore
|
21c3dbf611
|
Added regression for template project
|
2022-05-02 23:23:45 -06:00 |
|
tangxifan
|
9bd66d531e
|
[Test] Deploy the new test case to basic regression tests
|
2022-04-13 16:06:27 +08:00 |
|
tangxifan
|
3e3a65223c
|
[Test] Deploy new test case to basic regression tests
|
2022-03-20 11:04:07 +08:00 |
|
tangxifan
|
a615c9d4e3
|
[Test] Rename test cases
|
2022-02-24 09:43:41 -08:00 |
|
tangxifan
|
b27a04eb24
|
[Test] Now test case has a config done CCFF
|
2022-02-23 22:07:11 -08:00 |
|
tangxifan
|
cf31879b20
|
[Test] Deploy new test to basic regression tests
|
2022-02-23 16:03:56 -08:00 |
|
tangxifan
|
68644ea0f6
|
[Test] Add the new test to basic regression tests
|
2022-02-18 15:44:07 -08:00 |
|
tangxifan
|
fe9e0ff977
|
[Test] Add the new test to basic regression tests
|
2022-02-18 15:38:53 -08:00 |
|
tangxifan
|
85c893c94c
|
[Test] Add new test to basic regression tests
|
2022-02-18 15:30:08 -08:00 |
|
tangxifan
|
43d852d8a1
|
[Test] Add the bus group test case to basic regression tests
|
2022-02-18 12:27:25 -08:00 |
|
tangxifan
|
d667102a43
|
[Test] Add new test case to regression tests
|
2022-02-14 15:58:53 -08:00 |
|
tangxifan
|
0268814fc6
|
[Test] Splitting counter benchmarks into 2 categories; One has Verilog-to-Verification tests, while the other has only Verilog-to-Bitstream tests
|
2022-02-14 12:20:56 -08:00 |
|
tangxifan
|
27ac2fafe5
|
[Test] Add the new test case to regression tests
|
2022-02-01 13:45:46 -08:00 |
|
tangxifan
|
9871fe88fb
|
[Test] Typo fix
|
2022-01-31 13:03:45 -08:00 |
|
tangxifan
|
da8fc0f5d4
|
[Test] Add a new test case to validate ``--use_relative_path``
|
2022-01-31 13:02:19 -08:00 |
|
tangxifan
|
a9042318cf
|
[Test] Deploy the test case to regression tests
|
2022-01-26 11:26:17 -08:00 |
|
tangxifan
|
11e045992d
|
[Test] Now only compare on the golden netlist changes to branch
|
2022-01-25 21:24:10 -08:00 |
|
tangxifan
|
c2c827ee10
|
[Script] Fix a bug in git-diff for regression tests
|
2022-01-25 20:27:41 -08:00 |
|
tangxifan
|
fedb1bd2e3
|
[Test] Add new testcases to validate correctness of the testbenches/Verilog netlists without time stamp
|
2022-01-25 16:41:36 -08:00 |
|
tangxifan
|
5c0f63ddd9
|
[Test] Update regression tests for the new test about ``--no_time_stamp``
|
2022-01-25 16:30:48 -08:00 |
Aram Kostanyan
|
397f2e71f1
|
Added 'basic_tests/explicit_multi_verilog_files' task and deployed it to CI. Reverted previous commit chenges in 'benchmark_sweep/iwls2005' task.
|
2022-01-19 20:43:26 +05:00 |
Awais Abbas
|
469b3a960c
|
basic reg test updated
|
2022-01-14 15:44:26 +05:00 |
|
Awais Abbas
|
793e40cb95
|
basic_reg test for yosys-only flow added in OpenFPGA regression test scripts
|
2022-01-14 15:39:26 +05:00 |
|
tangxifan
|
628191da5f
|
[Test] Add new test case (DSP with registers) into FPGA-Verilog regression tests
|
2022-01-02 20:21:58 -08:00 |
nadeemyaseen-rs
|
236910cde4
|
Merge remote-tracking branch 'upstream/master' into update_from_upstream
|
2021-12-09 00:00:21 +05:00 |
coolbreeze413
|
b86bd1ca68
|
re-enable counter_5clock,sdc_controller, lut_adder tests
|
2021-11-19 18:06:06 +05:30 |
|
nadeemyaseen-rs
|
1ea56b2d18
|
Merge remote-tracking branch 'upstream/master' into update_from_upstream
|
2021-11-18 00:00:55 +05:00 |
|
coolbreeze413
|
840fa399c6
|
enable single counter test (fails, needs debug)
|
2021-11-09 21:36:33 +05:30 |
|
Aram Kostanyan
|
a707226ba6
|
Added 'basic_tests/verific_test' test case into regression tests suite.
|
2021-11-01 18:33:33 +05:00 |
|
tangxifan
|
ff264c00a2
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
|
2021-10-31 11:51:34 -07:00 |
|
tangxifan
|
18bab18032
|
[Test] Disable all the quicklogic tests due to missing support in Yosys v0.10 release
|
2021-10-30 13:20:58 -07:00 |
|
tangxifan
|
2bf203cd00
|
[Test] Deploy the new test to basic regression test
|
2021-10-11 09:54:39 -07:00 |
|
tangxifan
|
982a324e0d
|
[Test] Temporarily disable some tests; Will go back later
|
2021-10-10 23:30:50 -07:00 |
|
tangxifan
|
8f9e564cd5
|
[Test] Add the new test to basic regression test
|
2021-10-09 20:45:23 -07:00 |
|
tangxifan
|
554018449e
|
[Test] Update regression test script
|
2021-10-06 12:10:37 -07:00 |
|
tangxifan
|
064ac478f3
|
[Test] Deploy news test to fpga-bitstream regression tests
|
2021-10-05 19:01:03 -07:00 |
|
tangxifan
|
b21f212031
|
[Test] Replace the multi-region test with the fabric key test because the mutli region of shift-register bank is sensitive to the correctness of fabric key
|
2021-10-05 11:39:53 -07:00 |
|
tangxifan
|
492db50efe
|
[Test] Deploy the new test to basic regression tests
|
2021-10-05 10:59:26 -07:00 |
|
tangxifan
|
13c31cb89c
|
[Test] Deploy the qlbanksr_wlr to basic regression tests
|
2021-10-04 16:37:49 -07:00 |
|
tangxifan
|
7f75c2b619
|
[Test] Deploy shift register -based QL memory bank test case to basic regression test
|
2021-10-03 16:06:44 -07:00 |