tangxifan
|
153f1b5090
|
[core] update vtr
|
2023-03-06 16:07:11 -08:00 |
|
tangxifan
|
9823983b30
|
[core] debuggign
|
2023-03-06 15:57:37 -08:00 |
|
tangxifan
|
1633279c65
|
[core] fixed a bug in building edges for nodes
|
2023-03-06 14:50:28 -08:00 |
|
tangxifan
|
953625b1ca
|
[core] format
|
2023-03-05 22:32:05 -08:00 |
|
tangxifan
|
de1e300ec7
|
[core] now resize rr_node for clock graph is working
|
2023-03-05 22:21:55 -08:00 |
|
tangxifan
|
81e9187aac
|
[core] debugging
|
2023-03-03 22:55:14 -08:00 |
|
tangxifan
|
4423d917fa
|
[core] debugging
|
2023-03-03 18:00:43 -08:00 |
|
tangxifan
|
29ee6e7136
|
[core] debugging
|
2023-03-03 17:33:53 -08:00 |
|
tangxifan
|
59af073792
|
[ci] remove unnecessary checkout on submodules
|
2023-03-03 16:58:32 -08:00 |
|
tangxifan
|
5a43b451c1
|
[core] debugging
|
2023-03-03 16:56:20 -08:00 |
|
tangxifan
|
233a566774
|
Merge pull request #1082 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2023-03-03 16:29:28 -08:00 |
|
tangxifan
|
b009798ddb
|
Merge branch 'xt_clk_arch' of github.com:lnis-uofu/OpenFPGA into xt_clk_arch
|
2023-03-03 16:25:32 -08:00 |
|
tangxifan
|
304925b5ca
|
[script] update cmakelist to sync up latest compilation options in VTR
|
2023-03-03 16:24:48 -08:00 |
github-actions[bot]
|
0bdc9bab12
|
Updated Patch Count
|
2023-03-04 00:02:33 +00:00 |
|
tangxifan
|
19e41c6acd
|
Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into xt_clk_arch
|
2023-03-03 15:45:01 -08:00 |
|
tangxifan
|
d3de6e3bcd
|
[lib] update vtr
|
2023-03-03 15:31:26 -08:00 |
|
tangxifan
|
eb5da0ea98
|
Merge pull request #1079 from lnis-uofu/dependabot/submodules/yosys-plugins-ab3e14f
Bump yosys-plugins from `ae92491` to `ab3e14f`
|
2023-03-03 15:29:08 -08:00 |
|
tangxifan
|
0d5b9f1be7
|
Merge pull request #1080 from lnis-uofu/dependabot/submodules/yosys-9747e55
Bump yosys from `8216b23` to `9747e55`
|
2023-03-03 15:28:49 -08:00 |
|
tangxifan
|
c4ad21451c
|
[core] debugging
|
2023-03-02 21:54:48 -08:00 |
|
tangxifan
|
fd1c4039d3
|
[test] typo
|
2023-03-02 21:37:24 -08:00 |
|
tangxifan
|
98d8c75d86
|
[code] format
|
2023-03-02 21:36:08 -08:00 |
|
tangxifan
|
02b50e3464
|
[lib] now clock spine requires explicit definition of track type and direction when coordinate is vague
|
2023-03-02 21:33:32 -08:00 |
|
tangxifan
|
b9f7c72a96
|
[test] fixed some bugs in arch
|
2023-03-02 18:16:59 -08:00 |
|
tangxifan
|
46510388be
|
[core] now fabric generator can wire clock ports to routing blocks
|
2023-03-02 12:33:26 -08:00 |
dependabot[bot]
|
eb5aa5f5ae
|
Bump yosys from `8216b23` to `9747e55`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `8216b23` to `9747e55`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](8216b23fb7...9747e55d95)
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2023-03-02 08:00:16 +00:00 |
|
tangxifan
|
974263f0fa
|
[core] dev
|
2023-03-01 23:27:29 -08:00 |
|
tangxifan
|
099d9f32f4
|
[core] dev
|
2023-03-01 16:08:15 -08:00 |
|
dependabot[bot]
|
c39356d302
|
Bump yosys-plugins from `ae92491` to `ab3e14f`
Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `ae92491` to `ab3e14f`.
- [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases)
- [Commits](ae92491a67...ab3e14fbc6)
---
updated-dependencies:
- dependency-name: yosys-plugins
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2023-03-01 08:01:24 +00:00 |
|
tangxifan
|
60ff298987
|
[lib] add new feature to enable clock tree connection to global ports of tiles
|
2023-02-28 22:36:41 -08:00 |
|
tangxifan
|
5917446fbe
|
[arch] code format
|
2023-02-28 22:01:49 -08:00 |
|
tangxifan
|
780dec6b1b
|
[test] add a new test to validate the programmable clock arch
|
2023-02-28 21:46:57 -08:00 |
|
tangxifan
|
9baaf9ea06
|
[core] fix compiler warnings
|
2023-02-28 20:40:14 -08:00 |
|
tangxifan
|
7732907623
|
[core] format
|
2023-02-28 17:01:11 -08:00 |
|
tangxifan
|
2ff8fb8737
|
[core] wrapping up clock routing command
|
2023-02-28 16:52:54 -08:00 |
|
tangxifan
|
bd2608d3e0
|
[core] dev
|
2023-02-28 15:41:37 -08:00 |
|
tangxifan
|
6f2572324e
|
[core] developing route clock rr_graph command
|
2023-02-28 11:52:38 -08:00 |
|
tangxifan
|
8d5c21b14d
|
[core] code format
|
2023-02-27 23:00:15 -08:00 |
|
tangxifan
|
2735b708d3
|
[core] reworked the tapping XML syntax
|
2023-02-27 22:59:44 -08:00 |
|
tangxifan
|
ff69664c14
|
[core] syntax
|
2023-02-27 22:39:12 -08:00 |
|
tangxifan
|
d4e19edc71
|
[core] finishing up clock rr_graph appending
|
2023-02-27 22:31:16 -08:00 |
|
tangxifan
|
9f20d2e639
|
[lib] now clock arch supports tap points
|
2023-02-27 22:06:13 -08:00 |
|
tangxifan
|
3a40c5e15f
|
[lib] update example of clock arch definition
|
2023-02-27 21:49:14 -08:00 |
|
tangxifan
|
2df1609616
|
[core] add a new API to get pin index from a tile
|
2023-02-27 21:44:00 -08:00 |
|
tangxifan
|
0dfe96bcf1
|
[core] dev
|
2023-02-27 19:37:49 -08:00 |
|
tangxifan
|
7d0c23c675
|
[lib] new api for lowest level clock connections
|
2023-02-27 15:16:23 -08:00 |
|
tangxifan
|
b3dec93eb9
|
[core] code format
|
2023-02-27 15:12:59 -08:00 |
|
tangxifan
|
9ec4d690db
|
[core] clock edges interconnecting clock tracks across levels
|
2023-02-27 15:10:36 -08:00 |
|
tangxifan
|
b6eace8fac
|
[core] now switch id is linked in clock network
|
2023-02-27 13:10:54 -08:00 |
|
tangxifan
|
cae05a14e1
|
[core] dev
|
2023-02-26 23:10:50 -08:00 |
|
tangxifan
|
009d711ba5
|
[core] code format
|
2023-02-26 22:23:41 -08:00 |