tangxifan
|
a3e7133d63
|
Merge branch 'master' into wire_lut_test
|
2022-09-29 16:02:18 -07:00 |
|
tangxifan
|
ce0fbe1765
|
[test] fixed a few bugs
|
2022-09-29 15:32:31 -07:00 |
|
tangxifan
|
9bc9b61d35
|
[test] fixed a few bugs
|
2022-09-29 15:11:30 -07:00 |
|
tangxifan
|
f5e7ec4dd1
|
[test] add a new test case to validate wire lut case
|
2022-09-29 14:28:59 -07:00 |
|
tangxifan
|
3f8e2ade2e
|
[script] update missing scripts required by pb_pin_fixup test cases
|
2022-09-29 13:39:46 -07:00 |
|
tangxifan
|
49fa783914
|
[script] now suggest to skip pb_pin_fixup step in example scripts for most test cases
|
2022-09-29 10:45:27 -07:00 |
|
tangxifan
|
79b260f5e1
|
[arch] update missing arch
|
2022-09-21 16:52:32 -07:00 |
|
tangxifan
|
b1f8cdab3c
|
[test] update missing arch files which are not placed in the openfpga_flow/vpr_arch
|
2022-09-21 15:28:56 -07:00 |
|
tangxifan
|
b532bca9d2
|
[script] update golden outputs: see no changes in fabric netlists; accept changes in testbenches and bitstreams which comes from the random pin assignment
|
2022-09-21 10:54:16 -07:00 |
|
tangxifan
|
36603f9772
|
Merge branch 'master' into vtr_upgrade
|
2022-09-20 21:08:06 -07:00 |
|
tangxifan
|
b8f1520367
|
[test] fixed a bug
|
2022-09-20 18:12:23 -07:00 |
|
tangxifan
|
4e254a304d
|
[test] now golden netlists have no relationship with OPENFPGA_PATH
|
2022-09-20 18:10:52 -07:00 |
|
tangxifan
|
5e23be19a5
|
[test] now the test case that generates golden netlist use a special openfpga arch file which contains no soft paths
|
2022-09-20 18:07:31 -07:00 |
|
tangxifan
|
1b0b50b928
|
[test] update golden netlist
|
2022-09-20 16:04:05 -07:00 |
|
tangxifan
|
b630d60b7e
|
[test] update arch bitstream and force a pin placement for the test case where external bistream is fixed
|
2022-09-20 14:14:18 -07:00 |
|
tangxifan
|
37c5056d6a
|
[test] now use a fixed routing channel width for quicklogic tests
|
2022-09-20 12:25:40 -07:00 |
|
tangxifan
|
846ca26311
|
[test] enable block usage information output when running vpr. Otherwise some testcases miss the information for QoR checks
|
2022-09-20 12:08:24 -07:00 |
|
tangxifan
|
40663f956c
|
[test] relax counter128 required routing width from 50 to 60; Seem that VTR has some loss in routability
|
2022-09-19 21:55:15 -07:00 |
|
tangxifan
|
10e86d334a
|
[test] add test cases to validate the various layouts where I/Os are in the center of the grid
|
2022-09-16 10:29:19 -07:00 |
|
tangxifan
|
330785635d
|
[test] now use a bigger fabric for the test case on custom I/O location
|
2022-09-13 17:53:33 -07:00 |
|
tangxifan
|
0d6e4e3979
|
[test] add a new example for the repack options
|
2022-09-12 16:21:49 -07:00 |
|
tangxifan
|
1ab7590603
|
[test] added a new test case to
|
2022-09-09 16:59:06 -07:00 |
|
tangxifan
|
d4523e819c
|
[test] fixed a bug
|
2022-09-08 16:55:50 -07:00 |
|
tangxifan
|
d76f3e3b6c
|
[test] fixed the bug
|
2022-09-08 16:34:23 -07:00 |
|
tangxifan
|
218e6d0a47
|
[arch] fixed syntax errors
|
2022-09-08 16:31:52 -07:00 |
|
tangxifan
|
a840aeea7a
|
[test] add a new test to validate custom I/O location syntax and deploy to basic regression tests
|
2022-09-08 16:27:11 -07:00 |
|
tangxifan
|
477e2119d7
|
[test] remove abs paths in golden outputs without time stamps
|
2022-09-06 15:24:43 -07:00 |
|
tangxifan
|
93ab992187
|
[test] update golden outputs without time stamps
|
2022-09-06 14:59:00 -07:00 |
|
tangxifan
|
561d0a6545
|
[test] add more test case to track golden outputs for representative fpga sizes
|
2022-09-06 14:04:23 -07:00 |
|
tangxifan
|
c48f750f86
|
[test] now reduce the size for ql memory bank from 96x96 to 72x72; 96x96 requires >15G memory which exceeds github runner machine's RAM limit
|
2022-09-01 20:10:29 -07:00 |
|
tangxifan
|
51dc082bd4
|
[test] force a fixed routing chan W for no time stamp test case
|
2022-09-01 15:02:40 -07:00 |
|
tangxifan
|
d86eb04c5d
|
[test] now no timestamp test case covers gsb files
|
2022-09-01 14:03:51 -07:00 |
|
tangxifan
|
069e2b00b1
|
[test] add more test cases to validate gsb options
|
2022-08-29 22:03:06 -07:00 |
|
tangxifan
|
8b17bf1b1c
|
[test] add a new test case to validate that .act file is not required when power analysis flow is off
|
2022-08-01 18:44:47 -07:00 |
|
tangxifan
|
35fe858035
|
[test] fixed a few bugs
|
2022-07-28 12:06:16 -07:00 |
|
tangxifan
|
ca9122ddb9
|
[test] fixed a bug
|
2022-07-28 11:57:47 -07:00 |
|
tangxifan
|
ec31e124b7
|
[test] reworked test case on pcf2place
|
2022-07-28 11:51:56 -07:00 |
taoli4rs
|
cfc0d08060
|
Add constrain_pin_location command in openfpga; add full flow test.
|
2022-07-20 11:51:00 -07:00 |
|
tangxifan
|
9832722056
|
[test] now add QuickLogic memory bank to fpga bitstream regression tests
|
2022-05-25 11:42:32 +08:00 |
|
tangxifan
|
86347a9d49
|
[test] move generate_bitstream to another directory. Ready to test generate bitstream across different configuration protocols
|
2022-05-25 11:19:49 +08:00 |
|
tangxifan
|
6719a9aa26
|
[test] update golden netlists/testbenches etc.
|
2022-05-22 13:03:01 +08:00 |
|
tangxifan
|
22c4d72358
|
[test] add a test case to validate negative edge-triggered ff
|
2022-05-09 16:57:42 +08:00 |
Ganesh Gore
|
522982c9ba
|
Adde vtr_benchmarks_template for demo
|
2022-05-06 22:40:36 -06:00 |
|
Ganesh Gore
|
275cda081e
|
[Bugfix] Typo
|
2022-05-05 08:40:21 -06:00 |
|
Ganesh Gore
|
e845b62322
|
Update regession tasks
|
2022-05-05 01:46:19 -06:00 |
|
Ganesh Gore
|
21c3dbf611
|
Added regression for template project
|
2022-05-02 23:23:45 -06:00 |
|
Ganesh Gore
|
9891e42f7a
|
Added template task
|
2022-05-02 11:49:16 -06:00 |
|
tangxifan
|
efc25aa66e
|
[Script] Fixed a bug in wrong paths
|
2022-04-13 16:04:33 +08:00 |
|
tangxifan
|
5beefda3bd
|
[Test] Add a new test case to validate the fix_pins option
|
2022-04-13 15:55:21 +08:00 |
|
tangxifan
|
f8845f7d3a
|
[Test] Add a test case to validate separated clock pins in global port
|
2022-03-20 11:02:07 +08:00 |
|
tangxifan
|
fdaf97e60d
|
[Test] Update test case by using GPIO with config_done signals
|
2022-02-24 09:49:34 -08:00 |
|
tangxifan
|
a615c9d4e3
|
[Test] Rename test cases
|
2022-02-24 09:43:41 -08:00 |
|
tangxifan
|
b27a04eb24
|
[Test] Now test case has a config done CCFF
|
2022-02-23 22:07:11 -08:00 |
|
tangxifan
|
245c7b1e45
|
[Test] Add a new test case to validate config enable signal in preconfigured testbenches
|
2022-02-23 16:02:00 -08:00 |
|
tangxifan
|
e33ba667e4
|
[Test] Add missing file
|
2022-02-20 10:59:44 -08:00 |
|
tangxifan
|
f30de1085c
|
[Test] Cover all the related testcase about bus group
|
2022-02-19 23:33:16 -08:00 |
|
tangxifan
|
b4202f52b4
|
[Test] debugging
|
2022-02-19 23:26:29 -08:00 |
|
tangxifan
|
785bb1633d
|
[Test] trying to see if we support busgroup per benchmark in task configuration file
|
2022-02-19 23:23:36 -08:00 |
|
tangxifan
|
7645d5332d
|
[Test] Update bug group examples on the big endian support
|
2022-02-18 23:09:03 -08:00 |
|
tangxifan
|
f0ce1e79a3
|
[Test] Added a new test to validate bus group in full testbench
|
2022-02-18 15:43:21 -08:00 |
|
tangxifan
|
223575cf3e
|
[Test] Added a new test for bus group on full testbenches
|
2022-02-18 15:33:29 -08:00 |
|
tangxifan
|
5ab84e1861
|
[Test] Add a new test for bus group
|
2022-02-18 15:29:33 -08:00 |
|
tangxifan
|
b4d59fdd1e
|
[Test] Update bus group file due to little and big endian conversion during yosys/vpr
|
2022-02-18 15:02:08 -08:00 |
|
tangxifan
|
36543f7f2f
|
[Script] Support simplified rewriting for Yosys on output verilog
|
2022-02-18 14:54:39 -08:00 |
|
tangxifan
|
8ba3d06392
|
[Test] Fixed bugs in simulation settings
|
2022-02-18 12:36:22 -08:00 |
|
tangxifan
|
a4d5172b7c
|
[Test] Fixed bugs that causes VPR failed
|
2022-02-18 12:31:29 -08:00 |
|
tangxifan
|
7176037bc4
|
[Test] Added a new test about bus group
|
2022-02-18 12:26:00 -08:00 |
|
tangxifan
|
f02f3c10d4
|
[Test] Fix bugs on the remaining implicit verilog test cases
|
2022-02-15 16:49:15 -08:00 |
|
tangxifan
|
1370be0817
|
[Script] Fixing bugs
|
2022-02-15 16:44:51 -08:00 |
|
tangxifan
|
8be0868a3b
|
[Test] Update test case which uses counter benchmarks: adding pin constraints
|
2022-02-15 16:29:06 -08:00 |
|
tangxifan
|
f002c79a61
|
[Test] Adapt pin constraints due to changes in pin names
|
2022-02-15 16:06:46 -08:00 |
|
tangxifan
|
b533fd17d5
|
[Test] Rework pin constraints that cause problems
|
2022-02-15 15:41:16 -08:00 |
|
tangxifan
|
9ef7ad64d8
|
[Test] Simplify paths
|
2022-02-15 15:35:21 -08:00 |
|
tangxifan
|
d0fe8d96fa
|
[Test] Update template scripts and assoicated test cases by offering more options
|
2022-02-14 16:03:48 -08:00 |
|
tangxifan
|
70363effa4
|
[Test] Add a new test to validate 8-bit counters using full testbenches
|
2022-02-14 15:57:55 -08:00 |
|
tangxifan
|
7ef808cbe4
|
[Test] Update pin constraints for different counter benchmarks
|
2022-02-14 15:28:03 -08:00 |
|
tangxifan
|
570c1b10dc
|
[Test] Add dedicated pin constraints for counter designs
|
2022-02-14 13:54:48 -08:00 |
|
tangxifan
|
85011824e2
|
[Test] Enable Verilog-to-Verification flow for counter8 benchmarks
|
2022-02-14 13:15:55 -08:00 |
|
tangxifan
|
6630c17c23
|
[Test] Use preconfigured testbench template to run counter8 tests
|
2022-02-14 13:07:31 -08:00 |
|
tangxifan
|
da3f9ccb80
|
[Test] Truncating counter designs in each task
|
2022-02-14 12:22:19 -08:00 |
|
tangxifan
|
0268814fc6
|
[Test] Splitting counter benchmarks into 2 categories; One has Verilog-to-Verification tests, while the other has only Verilog-to-Bitstream tests
|
2022-02-14 12:20:56 -08:00 |
|
tangxifan
|
532af96243
|
[Test] Add a new testcase to validate ``--use_relative_path`` in preconfigured testbench
|
2022-02-01 13:44:47 -08:00 |
|
tangxifan
|
da8fc0f5d4
|
[Test] Add a new test case to validate ``--use_relative_path``
|
2022-01-31 13:02:19 -08:00 |
|
tangxifan
|
f8ef3df560
|
[Test] Now use 4x4 fabric in testing write_rr_gsb commands
|
2022-01-26 11:41:48 -08:00 |
|
tangxifan
|
3b7588cd48
|
[Test] Rename test case to be consistent with the name of options
|
2022-01-26 11:25:54 -08:00 |
|
tangxifan
|
6b26ed0819
|
[Test] Add test cases on writing gsb files
|
2022-01-26 11:22:39 -08:00 |
|
tangxifan
|
23795d6474
|
[Test] Update golden netlists
|
2022-01-25 20:37:08 -08:00 |
|
tangxifan
|
a9e6b7c12e
|
[FPGA-Bitstream] Remove version numbers when ``--no_time_stamp`` is enabled
|
2022-01-25 20:33:49 -08:00 |
|
tangxifan
|
fedb1bd2e3
|
[Test] Add new testcases to validate correctness of the testbenches/Verilog netlists without time stamp
|
2022-01-25 16:41:36 -08:00 |
|
tangxifan
|
6e778a74ee
|
[Test] Add golden reference for files outputted without time stamp
|
2022-01-25 16:24:25 -08:00 |
|
tangxifan
|
2bee59c6ca
|
[Test] Add the testcase to validate ``--no_time_stamp``
|
2022-01-25 16:21:15 -08:00 |
|
tangxifan
|
dd803dd1de
|
[Test] Remove unused tests
|
2022-01-25 16:16:58 -08:00 |
Aram Kostanyan
|
758453f725
|
Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
|
2022-01-21 02:21:00 +05:00 |
|
Aram Kostanyan
|
397f2e71f1
|
Added 'basic_tests/explicit_multi_verilog_files' task and deployed it to CI. Reverted previous commit chenges in 'benchmark_sweep/iwls2005' task.
|
2022-01-19 20:43:26 +05:00 |
|
Aram Kostanyan
|
bd158311c5
|
Fixed typo in documentation and updated 'benchmark_sweep/iwls2005' task to use list of HDL files for 'iwls2005/ethernet' benchmark.
|
2022-01-18 14:07:41 +05:00 |
|
Aram Kostanyan
|
588ee14920
|
Merge branch 'master' into issue-483
|
2022-01-18 13:38:12 +05:00 |
|
Aram Kostanyan
|
6a4cc340a3
|
Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
|
2022-01-17 13:21:29 +05:00 |
Awais Abbas
|
598c5e6b75
|
Test case for yosys-only flow added
|
2022-01-14 15:37:47 +05:00 |
|
tangxifan
|
824a03bdca
|
[Flow] Patch new test case
|
2022-01-02 20:20:36 -08:00 |
|
tangxifan
|
55da99f4ca
|
[Flow] Add a new test case to validate DSP with registers
|
2022-01-02 20:08:23 -08:00 |
nadeemyaseen-rs
|
06fb4b0ece
|
Merge remote-tracking branch 'upstream/master' into update_from_upstream
|
2021-11-25 00:00:22 +05:00 |
coolbreeze413
|
31379062e3
|
remove minor comments
|
2021-11-18 18:40:15 +05:30 |
|
nadeemyaseen-rs
|
1ea56b2d18
|
Merge remote-tracking branch 'upstream/master' into update_from_upstream
|
2021-11-18 00:00:55 +05:00 |
|
coolbreeze413
|
91094305bd
|
enable all tests except 15 and 19
|
2021-11-17 20:56:12 +05:30 |
|
coolbreeze413
|
840fa399c6
|
enable single counter test (fails, needs debug)
|
2021-11-09 21:36:33 +05:30 |
|
Aram Kostanyan
|
b332a5a1b4
|
Added 'basic_tests/verific_test' test-case.
|
2021-11-01 18:20:57 +05:00 |
|
tangxifan
|
ff264c00a2
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
|
2021-10-31 11:51:34 -07:00 |
|
tangxifan
|
7f999d03c6
|
[Test] update golden results for the vtr benchmarks due to Yosys v0.10 uprade
|
2021-10-30 18:05:39 -07:00 |
|
tangxifan
|
370e3fef83
|
[Test] Now use pre-configured testbench when verifying signal gen microbenchmarks
|
2021-10-30 18:03:59 -07:00 |
|
tangxifan
|
c8e9dfbeda
|
[Test] bug fix
|
2021-10-30 16:50:57 -07:00 |
|
tangxifan
|
a4cfc84930
|
[Test] Bug fix
|
2021-10-30 16:00:47 -07:00 |
|
tangxifan
|
335347a74f
|
[Test] Bug fix
|
2021-10-30 15:48:25 -07:00 |
|
tangxifan
|
be47e78289
|
[Arch] Change arch for Sapone test
|
2021-10-30 15:23:19 -07:00 |
|
tangxifan
|
ad5cce0ae8
|
[Test] Use frac_ff arch for SAPone; Otherwise Yosys cannot map reset signals
|
2021-10-30 15:11:07 -07:00 |
|
tangxifan
|
40d11a45d9
|
[Test] Disable ACE2 in implicit verilog test cases due to Yosys upgrade
|
2021-10-30 14:49:56 -07:00 |
|
tangxifan
|
16de60e943
|
[Test] Turn off ACE2 run in bitstream generation only flows
|
2021-10-30 12:31:14 -07:00 |
|
tangxifan
|
b2c4e3314e
|
[Test] Bug fix in test cases
|
2021-10-11 10:28:09 -07:00 |
|
tangxifan
|
8566e2a0cd
|
[Test] Renaming test case to follow naming convention as other fabric key test cases
|
2021-10-11 09:56:23 -07:00 |
|
tangxifan
|
b8b02d37d5
|
[Test] Added a new test case to validate the correctness of custom shift register chain through fabric key file
|
2021-10-11 09:53:23 -07:00 |
|
tangxifan
|
6122863548
|
[Test] Add a test case to validate the multi-shift-register-chain QL memory bank
|
2021-10-09 20:44:28 -07:00 |
|
tangxifan
|
a1eaacf5a8
|
[Test] Reduce the number of benchmarks in the test for fixed shift register clock frequency
|
2021-10-06 12:12:15 -07:00 |
|
tangxifan
|
b98a8ec718
|
[Test] Added the dedicated test case for fixed shift register clock frequency
|
2021-10-06 12:09:26 -07:00 |
|
tangxifan
|
189ade6c1e
|
[Test] Bug fix
|
2021-10-05 19:17:34 -07:00 |
|
tangxifan
|
f74ea5d39a
|
[Test] Use the new openfpga shell script in don't care bit tests
|
2021-10-05 19:14:44 -07:00 |
|
tangxifan
|
50604e4589
|
[Test] move test cases
|
2021-10-05 19:02:43 -07:00 |
|
tangxifan
|
fed6c133b1
|
[Test] Add new tests to validate the correctness of bitstream files with don't care bits
|
2021-10-05 18:59:33 -07:00 |
|
tangxifan
|
b21f212031
|
[Test] Replace the multi-region test with the fabric key test because the mutli region of shift-register bank is sensitive to the correctness of fabric key
|
2021-10-05 11:39:53 -07:00 |
|
tangxifan
|
52569f808e
|
[Test] Added a test case for QuickLogic memory bank using shift registers in multiple region
|
2021-10-05 10:57:33 -07:00 |
|
tangxifan
|
fa1908511d
|
[Test] Added a new test case to validate QuickLogic memory using shift registers with WLR control
|
2021-10-04 16:36:20 -07:00 |
|
tangxifan
|
dda147e234
|
[Flow] Add an example simulation setting file for defining programming shift register clocks
|
2021-10-01 11:04:23 -07:00 |
|
tangxifan
|
89a97d83bd
|
[Test] Added a new test case for the shift register banks in QuickLogic memory banks
|
2021-09-29 16:28:06 -07:00 |
|
tangxifan
|
4400dae108
|
[Test] Bug fix in the wrong arch name
|
2021-09-28 11:40:25 -07:00 |
|
tangxifan
|
dae3554fd4
|
[Test] Add a new test case for QL memory bank with flatten BL/WL buses using WLR signals
|
2021-09-28 11:27:49 -07:00 |
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tangxifan
|
655b195d8b
|
[Test] Added a test case to validate the correctness of QL memory bank where BL/WL are flatten on the top level
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2021-09-22 15:56:44 -07:00 |
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tangxifan
|
b0aaab9c03
|
[Test] Bug fix due to mismatches in device layout between fabric key and VPR settings
|
2021-09-22 11:32:13 -07:00 |
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tangxifan
|
abfa380333
|
[Test] Added a test case to validate the fabric key of 2-region QL memory bank
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2021-09-22 11:27:09 -07:00 |
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tangxifan
|
51fc222d61
|
[Test] Added a new test case for multi-region QL memory bank
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2021-09-22 10:01:33 -07:00 |
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tangxifan
|
1412121541
|
[Test] Added a new test to validate the fabric key parser for QL memory bank
|
2021-09-21 16:20:24 -07:00 |
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tangxifan
|
dc2d1d1c3c
|
[Test] Add a new test case to validate the correctness of fabric key file for ql memory bank
|
2021-09-21 15:42:20 -07:00 |
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tangxifan
|
60fc3ab36c
|
[Test] Added a new test case for the WLR memory bank
|
2021-09-20 11:20:36 -07:00 |
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tangxifan
|
b82cfdf555
|
[Test] Add the QL memory bank test to regression test cases
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2021-09-09 09:29:21 -07:00 |
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tangxifan
|
6adf439081
|
Merge remote-tracking branch 'upstream/master'
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2021-09-01 14:19:00 -07:00 |
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tangxifan
|
9f03ecb160
|
[Test] Patch test case due to the changes in counter benchmarks
|
2021-07-02 17:57:39 -06:00 |
|
tangxifan
|
64dcdaec61
|
[Test] Update all the tasks that use counter benchmark
|
2021-07-02 17:29:13 -06:00 |
|
tangxifan
|
3cbe266c44
|
[Test] Bug fix on the test case for multi-mode FF and pin constraints
|
2021-07-02 15:27:27 -06:00 |
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tangxifan
|
3aacce2a96
|
Merge branch 'pin_constraint_polarity' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity
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2021-07-02 14:04:42 -06:00 |
|
Ganesh Gore
|
edd5be2cae
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[CI] Added testcase for benchmark variable
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2021-07-02 12:51:34 -06:00 |
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tangxifan
|
5286f9ba25
|
[Test] Reworked the test case for k4n4 multi-mode FF architecture by including more counter benchmarking
|
2021-07-02 11:39:00 -06:00 |
ANDREW HARRIS POND
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006b54c4bc
|
ready for merge
|
2021-07-01 15:35:39 -06:00 |
|
ANDREW HARRIS POND
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8513b8a4ff
|
Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench
|
2021-07-01 15:29:39 -06:00 |
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ANDREW HARRIS POND
|
2567fbee05
|
ready to merge
|
2021-07-01 15:28:59 -06:00 |
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tangxifan
|
04ceeefb0a
|
Merge branch 'master' into verilog_testbench
|
2021-07-01 14:43:26 -06:00 |
|
ANDREW HARRIS POND
|
db9231c225
|
tests failing with initial blocks
|
2021-07-01 13:52:28 -06:00 |
komaljaved-rs
|
be14e4f448
|
added design_variables.yml
|
2021-07-01 16:31:42 +05:00 |
|
komaljaved-rs
|
6559f71082
|
added ci_scripts
|
2021-07-01 15:07:37 +05:00 |
|
tangxifan
|
83d177b13b
|
[Test] Deploy the newly added adder benchmarks to tests
|
2021-06-30 15:14:24 -06:00 |
|
tangxifan
|
9eeec05a1f
|
[Test] Bug fix
|
2021-06-29 19:55:07 -06:00 |
|
tangxifan
|
f32ffb6d61
|
[Test] Bug fix
|
2021-06-29 18:51:28 -06:00 |
|
tangxifan
|
c6089385b0
|
[Misc] Bug fix
|
2021-06-29 18:34:41 -06:00 |
|
tangxifan
|
5f5a03f17f
|
[Misc] Bug fix on test cases that were generating both full testbench and preconfigured testbenches
|
2021-06-29 18:28:38 -06:00 |
|
tangxifan
|
2c1692e6dc
|
[Test] Bug fix
|
2021-06-29 17:54:25 -06:00 |
|
tangxifan
|
30c2f597f2
|
[Test] Added two cases to validate testbench generation without self checking
|
2021-06-29 16:06:15 -06:00 |
|
tangxifan
|
6f0600e17f
|
[Test] Added two test cases for generating preconfigured fabric wrapper in different styles
|
2021-06-27 19:56:01 -06:00 |
|
tangxifan
|
477cba1c7e
|
Merge branch 'master' into verilog_testbench
|
2021-06-23 09:18:18 -06:00 |
|
tangxifan
|
f06017581c
|
[Test] Bug fix in counter micro benchmark tests
|
2021-06-22 16:33:50 -06:00 |
|
tangxifan
|
760570d883
|
[Test] Update counter test case for cover most counter HDL design
|
2021-06-21 18:13:18 -06:00 |
|
tangxifan
|
9c24a739be
|
[Test] Added a MAC benchmark sweeping test
|
2021-06-21 17:40:53 -06:00 |
Andrew Pond
|
3cfc42cdf9
|
added testbench CI
|
2021-06-15 14:16:31 -06:00 |
|
tangxifan
|
eed30605d7
|
[Test] patch test case
|
2021-06-09 15:20:55 -06:00 |
|
tangxifan
|
52c0ed571b
|
[Test] Patch test case to use proper template
|
2021-06-09 14:27:02 -06:00 |
|
tangxifan
|
c62666e7c3
|
[Test] Use proper template for some failing tests
|
2021-06-09 14:24:34 -06:00 |
|
tangxifan
|
462326aaa5
|
[Test] Update full testbench test case for flatten configuration protocol using 'write_full_testbench'
|
2021-06-07 21:50:00 -06:00 |
|
tangxifan
|
5ecd975ec7
|
[Test] Bug fix
|
2021-06-07 19:20:10 -06:00 |
|
tangxifan
|
9556f994b4
|
[Test] Use 'write_full_testbench' in all the memory bank -related test cases
|
2021-06-07 17:49:40 -06:00 |
|
tangxifan
|
a67196178e
|
[Test] Now use 'write_full_testbench' in configuration frame test cases
|
2021-06-07 13:58:15 -06:00 |
|
tangxifan
|
27fa15603a
|
[Tool] Patch test case due to changes in the template script
|
2021-06-04 18:17:47 -06:00 |
|
tangxifan
|
5f96d440ec
|
[Test] Deploy 'write_full_testbench' openfpga shell script to multi-headed configuration chain with auto-tuned fast configuration
|
2021-06-04 11:48:05 -06:00 |
|
tangxifan
|
ec203d3a5c
|
[Test] Deploy 'write_full_testbench' openfpga shell script to all the fast configuration chain test cases
|
2021-06-04 11:35:23 -06:00 |
|
tangxifan
|
2068291de0
|
[Test] Now deploy the 'write_full_testbench' openfpga shell script to all the configuration chain test cases
|
2021-06-04 11:32:49 -06:00 |
|
tangxifan
|
aa4e1f5f9a
|
[Test] Update test case which uses write_full_testbench openfpga shell script
|
2021-06-04 11:29:43 -06:00 |
|
tangxifan
|
ebe30fc070
|
[Test] Deploy write full testbench to multi-head configuration chain test case
|
2021-06-03 17:08:33 -06:00 |
|
tangxifan
|
1e9f6eb439
|
[Test] update configuration chain test to use new testbench
|
2021-06-03 15:53:27 -06:00 |
|
tangxifan
|
2baf3ddd2f
|
[Test] Add test cases for 'report_bitstream_distribution' command
|
2021-05-07 12:06:24 -06:00 |
|
tangxifan
|
f1658cb735
|
[Test] Deploy blinking to test cases
|
2021-05-06 15:17:45 -06:00 |
|
tangxifan
|
a5e40fbb21
|
Merge branch 'master' into micro_benchmarks
|
2021-04-28 14:27:58 -06:00 |
|
tangxifan
|
b72d4bd807
|
[Test] Update test case for 1kbit DPRAM architectures
|
2021-04-28 11:28:53 -06:00 |
|
tangxifan
|
5c729657ef
|
[Test] Bug fix in test case for DPRAM whose width = 2
|
2021-04-28 10:31:22 -06:00 |
|
tangxifan
|
0bec4b3f32
|
[Test] Update task configuration to use proper openfpgashell script
|
2021-04-27 23:34:42 -06:00 |
|
tangxifan
|
fdfbdc4613
|
[Test] Update task configuration files to use dedicated yosys script
|
2021-04-27 20:05:04 -06:00 |
|
tangxifan
|
b8ced5377f
|
[Test] Add a test case for i/o mapping writer
|
2021-04-27 14:41:15 -06:00 |
|
tangxifan
|
6291871faf
|
[Test] Added a test for the example architecture with 2x2 DSP blocks
|
2021-04-26 16:28:43 -06:00 |
|
tangxifan
|
80f98328df
|
[Test] Update test settings for architecture with fracturable DSP blocks
|
2021-04-24 15:16:50 -06:00 |
|
tangxifan
|
1c6b9a23d7
|
[Test] Add new test for multi-mode 16-bit DSP blocks
|
2021-04-24 13:29:29 -06:00 |
|
tangxifan
|
189c94ff19
|
[Test] Deploy new mac benchmarks to tests
|
2021-04-23 20:44:14 -06:00 |
|
tangxifan
|
784713e88a
|
[Test] Add golden results for IWLS2005 as a simple QoR check
|
2021-04-22 19:27:31 -06:00 |
|
tangxifan
|
1dcb8e39a9
|
[Test] Unlock more IWLS'2005 benchmarks in testing
|
2021-04-22 09:23:33 -06:00 |
|
tangxifan
|
61a473e479
|
[Test] Unlock more IWLS'2005 benchmarks under testing thanks to flexible FF mapping support
|
2021-04-21 22:56:19 -06:00 |
|
tangxifan
|
3a5c26c6a1
|
[Test] Update IWLS test by using new architecture and customize DFF techmap
|
2021-04-21 19:51:25 -06:00 |
|
tangxifan
|
8046b16c15
|
[Test] Remove restrictions in the multi-clock test case and deploy new microbenchmarks for testing
|
2021-04-21 14:04:34 -06:00 |
|
tangxifan
|
578d81b67a
|
[Test] Patch task configuration file
|
2021-04-19 16:15:00 -06:00 |