tangxifan
|
2dea97afb6
|
[Regression test] reduce runtime for k4n4 test in basic testing
|
2020-09-22 11:45:29 -06:00 |
|
tangxifan
|
2881312637
|
[Regression test] deploy k4 series test cases to CI
|
2020-09-22 11:43:34 -06:00 |
|
tangxifan
|
ea4dd410b7
|
[Regression Test] Add k4n4 fracturable lut test case to basic test
|
2020-09-22 11:41:36 -06:00 |
|
tangxifan
|
dad19cac9a
|
[Regression test] Add k4 series architecture: fracturable adder
|
2020-09-22 11:39:18 -06:00 |
|
tangxifan
|
dd192a2f54
|
[Architecture] Add a k4k4 openfpga architecture with carry chain for quick test
|
2020-09-22 11:34:23 -06:00 |
|
tangxifan
|
7a6f5a06f7
|
[Architecture] Add a k4n4 architecture with carry chain to quick test
|
2020-09-22 11:33:56 -06:00 |
Laboratory for Nano Integrated Systems (LNIS)
|
fba8dbe638
|
Merge pull request #89 from LNIS-Projects/dev
Regression test & architecture updates
|
2020-09-21 22:53:34 -06:00 |
|
tangxifan
|
aa5f5fc7e0
|
[Architecture] Bring back pin equivalence for no local routing architecture
|
2020-09-21 22:22:39 -06:00 |
|
tangxifan
|
26f1a5d9ec
|
[OpenFPGA Tool] Bug fix for repacking no local routing architecture
|
2020-09-21 22:22:03 -06:00 |
|
tangxifan
|
a8a269aa82
|
[Architecture] Temporary patch for the no local routing architecture
|
2020-09-21 19:51:23 -06:00 |
|
tangxifan
|
acf318f184
|
[Regression test] Bug fix in test case fabric_chain
|
2020-09-21 18:58:35 -06:00 |
|
tangxifan
|
e4291eb27e
|
[Regression Tests] Now use fixed device layout in test cases for best coverage
|
2020-09-21 18:44:13 -06:00 |
|
tangxifan
|
7a57cc9cf4
|
[Architecture] A new device layout to k4n4 to test untileable architecture
|
2020-09-21 18:36:50 -06:00 |
|
tangxifan
|
2bbfcb5753
|
[Architecture] Add a new device layout to k4n4 for testing tileable routing
|
2020-09-21 18:34:31 -06:00 |
|
tangxifan
|
e1c5947143
|
[Architecture] Add auto layout and fixed layout to architectures
|
2020-09-21 18:01:51 -06:00 |
|
tangxifan
|
936a164eee
|
[OpenFPGA flow] Add a new template script to use a fixed device layout
|
2020-09-21 17:48:28 -06:00 |
|
tangxifan
|
d7f8b3abad
|
[Architecture] Add k4 N4 untilable architecture
|
2020-09-21 17:44:37 -06:00 |
|
tangxifan
|
a83bc3f75c
|
[Regression tests] Add test cases for the fracturable LUT4 architecture and deploy it to CI
|
2020-09-21 17:38:16 -06:00 |
|
tangxifan
|
e9c0e90544
|
[Architecture] Add a VPR architectue using fracturable LUT4
|
2020-09-21 17:37:26 -06:00 |
|
tangxifan
|
60f328a2ab
|
[Architecture] Add openfpga architecture for a small k4 fracturable FPGA
|
2020-09-21 17:36:57 -06:00 |
|
Laboratory for Nano Integrated Systems (LNIS)
|
9a995d143e
|
Merge pull request #88 from LNIS-Projects/tangxifan-patch-1
Update issue templates
|
2020-09-20 19:43:16 -06:00 |
|
tangxifan
|
5d9228eb2e
|
Update bug_report.md
|
2020-09-20 17:24:29 -06:00 |
|
tangxifan
|
defb5dea4b
|
Update issue templates
|
2020-09-20 17:08:07 -06:00 |
|
tangxifan
|
dc11e84f6a
|
Merge pull request #87 from LNIS-Projects/dev
Transplant FPGA-SPICE to OpenFPGA
|
2020-09-20 17:05:33 -06:00 |
|
tangxifan
|
c6ac02d210
|
[FPGA-SPICE] Add VDD/VSS ports to SPICE subckt instanciation
|
2020-09-20 15:21:33 -06:00 |
|
tangxifan
|
e867e203f4
|
[Documentation] Use release mode in Docker settings
|
2020-09-20 15:00:56 -06:00 |
|
tangxifan
|
544c44fe46
|
[FPGA-SPICE] Add VDD and VSS port to module definition
|
2020-09-20 14:58:15 -06:00 |
|
tangxifan
|
615a24999a
|
[Documentation] Remove out-of-date description
|
2020-09-20 14:45:33 -06:00 |
|
tangxifan
|
460fef5807
|
[FPGA-Verilog] Rename files and functions to distinguish from FPGA-SPICE files and functions
|
2020-09-20 12:58:55 -06:00 |
|
tangxifan
|
222bc86cbf
|
[FPGA-SPICE] Add auxiliary SPICE netlist writer
|
2020-09-20 12:53:28 -06:00 |
|
tangxifan
|
06c0073a3e
|
[FPGA-SPICE] Add SPICE writer for fpga top module
|
2020-09-20 12:43:48 -06:00 |
|
tangxifan
|
1dfb3e06cc
|
[FPGA-SPICE] add SPICE writer for logic blocks
|
2020-09-20 12:38:24 -06:00 |
|
tangxifan
|
5e78e91fdf
|
[FPGA-SPICE] Add SPICE writer for routing blocks
|
2020-09-20 12:27:48 -06:00 |
|
tangxifan
|
0f25b52907
|
[FPGA-Verilog] code format fix
|
2020-09-20 12:18:22 -06:00 |
|
tangxifan
|
2fae311c8e
|
[FPGA-SPICE] Add SPICE writer for memories
|
2020-09-20 12:14:34 -06:00 |
|
tangxifan
|
f284f6f8d0
|
[OPENFPGA LIBRARY] change method names to be consistent with FPGA-SPICE needs
|
2020-09-20 12:03:10 -06:00 |
|
tangxifan
|
6801d260e9
|
[FPGA-SPICE] Add SPICE writer for LUT
|
2020-09-20 11:58:11 -06:00 |
|
tangxifan
|
0f9fce92b2
|
[FPGA-SPICE] Add SPICE writer for routing multiplexers
|
2020-09-20 11:49:02 -06:00 |
|
tangxifan
|
c7e3d97d1b
|
[FPGA-SPICE] Add supply voltage generator
|
2020-09-20 11:19:06 -06:00 |
|
tangxifan
|
15df9b3893
|
[FPGA-SPICE] Add SPICE subcircuit writer
|
2020-09-19 23:01:44 -06:00 |
|
tangxifan
|
82e137cbe4
|
[FPGA-SPICE] Add wire module SPICE writer
|
2020-09-19 19:31:16 -06:00 |
|
tangxifan
|
1b2762386c
|
[FPGA-SPICE] Bug fix for essential gate netlist writing
|
2020-09-19 16:52:30 -06:00 |
|
tangxifan
|
26a0a769ea
|
[FPGA-SPICE] Split essential gate SPICE netlists into separated files
|
2020-09-19 16:45:26 -06:00 |
|
tangxifan
|
e102e30d19
|
[FPGA-SPICE] Add support for AND/OR logic gate
|
2020-09-19 16:20:21 -06:00 |
|
tangxifan
|
482d90018f
|
[FPGA-SPICE] Create generic PMOS/NMOS instanciation function
|
2020-09-19 15:33:28 -06:00 |
|
tangxifan
|
3262ceb276
|
[FPGA-SPICE] Bug fix for pass gate transistor sizing
|
2020-09-19 15:24:40 -06:00 |
|
tangxifan
|
aa078f079c
|
[FPGA-SPICE] Restructured SPICE netlist writers for atom circuits to avoid large cpp files
|
2020-09-19 15:20:19 -06:00 |
|
tangxifan
|
f5dadca884
|
[FPGA-SPICE] Optimize the print-out of SPICE ports
|
2020-09-19 15:07:48 -06:00 |
|
tangxifan
|
51d423e4db
|
[FPGA-SPICE] Add pass-gate SPICE netlist writer
|
2020-09-19 14:59:00 -06:00 |
|
Laboratory for Nano Integrated Systems (LNIS)
|
882854585c
|
Merge pull request #86 from LNIS-Projects/dev
Misc Updates
|
2020-09-17 19:43:06 -06:00 |