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2,673 Commits 70 Branches 8 Tags 105 MiB
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2673 Commits

Author SHA1 Message Date
tangxifan 81965e75f6 [Architecture] Bug fix in DFF Verilog HDL 2020-09-24 14:53:21 -06:00
tangxifan 3b42fe94d6 [Architecture] Update external bitstream file 2020-09-24 14:41:44 -06:00
tangxifan 08838c4957 [Regression Test] Deploy new configuration chain test cases to CI 2020-09-24 14:36:39 -06:00
tangxifan 7fbccdd102 [Regression Tests] Add test cases for configuration chain using different DFF cells 2020-09-24 14:34:12 -06:00
tangxifan 178afb3c7f [Architecture] Add configuration chain architectures using different DFF cells 2020-09-24 14:23:27 -06:00
tangxifan 98d88dc686 [Architecture] Bug fix for vanilla memory organization 2020-09-24 14:13:48 -06:00
tangxifan efad0402c2 [Regression Test] Bug fix for CI errors 2020-09-24 13:55:41 -06:00
tangxifan e7906899dd [Regression test] Bug fix for fast configuration frame. Now should use a latch with reset 2020-09-24 13:53:12 -06:00
tangxifan e832d806c7 [Architecture] Add DFF Verilog netlist using standard naming convention 2020-09-24 13:50:59 -06:00
tangxifan 1b13e8ecb1 [Architecture] Bug fix in the SRAM Verilog 2020-09-24 12:26:13 -06:00
tangxifan 9d9cf6ee71 [Regression Test] Deploy new tests to CI 2020-09-24 12:20:18 -06:00
tangxifan ffd1a72d22 [Architecture] Add regression tests for the frame-based configuration using reset and set signals 2020-09-24 12:18:26 -06:00
tangxifan 539bb617f9 [Architecture] Add reset test case for frame based configuration 2020-09-24 12:17:18 -06:00
tangxifan 2add0406a7 [Architecture] Update architecture files for new latch naming 2020-09-24 12:14:03 -06:00
tangxifan fde15c4f88 [Regression Test] Add test for fast memory bank configuration using set signals 2020-09-24 12:13:35 -06:00
tangxifan 7238a2be03 [Architecture] Merge latch Verilog HDL to a unique file 2020-09-24 11:02:01 -06:00
tangxifan 48083d2276 [Regression Test] Adapt fast memory bank test case 2020-09-24 10:32:03 -06:00
tangxifan 83971bba41 [Architecture] Update cell ports for native SRAM cell 2020-09-24 10:31:31 -06:00
tangxifan e454467799 [Regression Test] Deploy memory bank test cases to CI 2020-09-24 10:26:10 -06:00
tangxifan 186f00edfc [Regression Test] Add test cases for memory bank using different SRAM cells 2020-09-24 10:25:03 -06:00
tangxifan 56c9aab190 [Architecture] Add architecture to use different SRAM cells for memory bank 2020-09-24 10:15:08 -06:00
tangxifan 6bb30ab33c [Architecture] Enrich SRAM Verilog HDL for flexible set/reset support 2020-09-24 10:02:51 -06:00
tangxifan 70a8c6dc29 [Regression Test] Add test case using active-low set to CI 2020-09-23 23:07:19 -06:00
tangxifan 10b6e1dc0d [Architecture] bug fix for active-low 2020-09-23 23:06:46 -06:00
tangxifan 5b0d451f0f [Regression Test] Add test case for configurable latch with active-low set 2020-09-23 23:04:10 -06:00
tangxifan 5d60b4ef8c [Architecture] Add openfpga architecture and Verilog HDL for configurable latch with active-low set 2020-09-23 23:02:49 -06:00
tangxifan 8e780635df [Regression Test] Rename test case in CI 2020-09-23 22:59:46 -06:00
tangxifan d0cef68242 [Regression test] Add test case for using resetb 2020-09-23 22:58:59 -06:00
tangxifan c7fc0178b0 [Architecture] Rename to be consist with other architectures 2020-09-23 22:57:06 -06:00
tangxifan 07198f6396 [Regression Test] Deploy smart configuration tests to CI 2020-09-23 22:08:30 -06:00
tangxifan 707300a6e4 [Architecture] Bug fix for using both reset and set architecture 2020-09-23 22:07:40 -06:00
tangxifan 77a1f99564 [Architecture] Bug fix for architecture using set only 2020-09-23 22:04:24 -06:00
tangxifan 46b12611a9 [OpenFPGA Tool] Bug fix for smart fast configuration 2020-09-23 22:04:07 -06:00
tangxifan fcf1ff418f [Architecture] Add Verilog for SRAM using set/reset 2020-09-23 21:53:38 -06:00
tangxifan 73e59d67af [Architecture] Add test case for fast configuration using set signals 2020-09-23 21:50:23 -06:00
tangxifan 349aa79069 [Regression test] Add test case for smart fast configuration 2020-09-23 21:49:38 -06:00
tangxifan 9331ef941d [Architecture] Add architecture that use both set and reset signals 2020-09-23 21:46:04 -06:00
tangxifan 7591060fbd [Architecture] Add configurable latch Verilog designs and assoicated architectures 2020-09-23 21:45:06 -06:00
tangxifan 8fa4fa1125 [Architecture] Add openfpga architecture using set signals for configurable latch 2020-09-23 21:39:31 -06:00
tangxifan 154c9045f6 [OpoenFPGA Tool] Bug fix for smart fast configuration 2020-09-23 21:38:42 -06:00
tangxifan c2c37d7555 [OpenFPGA Tool] Add more print-out for smart fast configuration 2020-09-23 21:34:23 -06:00
tangxifan f57fd273af [Documentation] Update documentation for smart fast configuration 2020-09-23 21:28:06 -06:00
tangxifan a3abf81afe [OpenFPGA Tool] Support on set signals and smart selection between reset and set signal for fast configuration 2020-09-23 21:25:06 -06:00
tangxifan 709a20a349 [Regression Test] Deploy new test to CI 2020-09-23 20:45:19 -06:00
tangxifan 05c2e652a4 [Regression Test] Add a new test case for using scan-chain ff in frame-based configuration protocol 2020-09-23 20:44:06 -06:00
tangxifan 2869eae8a9 [Architecture] Add openfpga architecture where scan-chain ff is used in frame-based configuration protocol 2020-09-23 20:43:15 -06:00
tangxifan fc60b18191 [Architecture] Now a regular flip-flop can be used in frame-based configuration 2020-09-23 20:41:49 -06:00
tangxifan 8b8ce22fd1 [OpenFPGA Tool] Bug fix for the edge trigger attribute in cirucit library 2020-09-23 20:37:28 -06:00
tangxifan 3d234d840b [Documentation] Update documentation for the edge triggered attribute 2020-09-23 20:31:11 -06:00
tangxifan 064678fe32 [OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol 2020-09-23 20:27:52 -06:00