3 Commits

Author	SHA1	Message	Date
Aram Kostanyan	758453f725	Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.	2022-01-21 02:21:00 +05:00
Aram Kostanyan	6a4cc340a3	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
tangxifan	9c24a739be	[Test] Added a MAC benchmark sweeping test	2021-06-21 17:40:53 -06:00