tangxifan
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646ee90937
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bring tileable gsb builder for rr_graph online
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2020-03-04 18:19:53 -07:00 |
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tangxifan
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4455615980
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adapt tileable routing channel detail builder
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2020-03-04 14:21:35 -07:00 |
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tangxifan
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6e83154703
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move rr_gsb and rr_chan to tileable rr_graph builder
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2020-03-04 14:14:28 -07:00 |
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tangxifan
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4b7d2221d1
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adapt rr_graph builder utilized functions and move rr_graph utils from openfpga to vpr
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2020-03-04 13:55:53 -07:00 |
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tangxifan
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524798799c
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start adapting tileable rr_graph builder. Bring channel node detail data structure online
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2020-03-04 11:21:34 -07:00 |
AurelienUoU
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aed3b01800
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Directlist extension bug fix
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2020-03-04 09:09:06 -07:00 |
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tangxifan
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9f13d3bc23
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Merge branch 'refactoring' into dev
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2020-03-03 12:31:20 -07:00 |
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tangxifan
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7fcd27e000
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now we give explicit instance name to each interconnect inside grid. Thus resolve the problem in sdc writer
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2020-03-03 12:29:58 -07:00 |
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tangxifan
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3241d8bd37
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put analysis sdc writer online. Minor bug in redudant '/' to be fixed
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2020-03-02 19:54:18 -07:00 |
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tangxifan
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037c7e5c43
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adapt top-level function for analysis SDC writer
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2020-03-02 17:58:44 -07:00 |
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tangxifan
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24f7416c71
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adapt analysis SDC writer for grids
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2020-03-02 17:15:01 -07:00 |
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tangxifan
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6474183539
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adapt analysis SDC writer for routing modules
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2020-03-02 14:29:58 -07:00 |
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tangxifan
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543cff58b9
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start porting analysis SDC writer
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2020-03-02 13:44:08 -07:00 |
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tangxifan
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7befcaba57
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Merge branch 'refactoring' into dev
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2020-03-02 11:22:58 -07:00 |
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tangxifan
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a17c14c363
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clean-up command addition and add fabric bitstream building to sample script
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2020-03-02 10:39:19 -07:00 |
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tangxifan
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9fe8ff51f9
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Merge branch 'refactoring' into dev
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2020-02-29 15:19:52 -07:00 |
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tangxifan
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aa66042dfb
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move simulation setting annotation to a separated source file
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2020-02-29 15:19:02 -07:00 |
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tangxifan
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cf25f1f339
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Merge branch 'refactoring' into dev
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2020-02-29 13:30:00 -07:00 |
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tangxifan
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7b18f7cd09
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now the auto select number of clocks in simulation is online
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2020-02-29 13:29:16 -07:00 |
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tangxifan
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3807a940f4
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fixed critical bugs in bitstream generation and now we pass microbenchmarks
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2020-02-28 16:45:50 -07:00 |
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tangxifan
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9fd184e3ab
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rm out-of-date script
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2020-02-28 15:42:18 -07:00 |
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tangxifan
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05ebd77d7d
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start debugging with micro benchmarks. Spot problem in local routing
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2020-02-28 15:41:32 -07:00 |
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tangxifan
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a6c2d2c7d1
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bug fixed for io location mapping
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2020-02-28 14:46:01 -07:00 |
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tangxifan
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80bb2baae5
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start verification and bug fixing
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2020-02-28 14:29:01 -07:00 |
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tangxifan
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542fadaaae
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allow users to use VPR critical path delay in OpenFPGA simulation
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2020-02-28 12:10:27 -07:00 |
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tangxifan
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de8425874c
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use user defined critical path delay in SDC generation
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2020-02-28 11:24:39 -07:00 |
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tangxifan
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092e10afda
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bring pnr sdc generator online and fixed minor bugs in bitstream writing
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2020-02-28 11:14:50 -07:00 |
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tangxifan
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e45fa18c4c
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adapt PnR SDC writer
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2020-02-28 10:06:35 -07:00 |
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tangxifan
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89c51b70e3
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split sdc option into two categories which will be called by different commands
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2020-02-28 09:48:58 -07:00 |
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tangxifan
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fdcb982903
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adapt pnr sdc grid writer
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2020-02-27 21:06:33 -07:00 |
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tangxifan
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b4ed931ac6
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adapt sdc routing writer
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2020-02-27 20:35:56 -07:00 |
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tangxifan
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d136ac236f
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adapt sdc memory utils
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2020-02-27 19:39:57 -07:00 |
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tangxifan
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78476ca774
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adapt sdc writer utils
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2020-02-27 19:36:28 -07:00 |
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tangxifan
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8322b1623d
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start porting SDC generator
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2020-02-27 19:30:36 -07:00 |
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tangxifan
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fc509aa2c1
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Merge branch 'refactoring' into dev
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2020-02-27 18:03:21 -07:00 |
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tangxifan
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65c81e14b2
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add simulation ini file writer
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2020-02-27 18:01:47 -07:00 |
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tangxifan
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ae899f3b11
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bug fixed for clock names
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2020-02-27 16:51:55 -07:00 |
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tangxifan
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9b769cd8e4
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bug fix for using renamed i/o names
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2020-02-27 16:37:20 -07:00 |
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tangxifan
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b010fc1983
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add warning to force formal_verification_top_netlist enabled
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2020-02-27 13:28:21 -07:00 |
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tangxifan
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078f72320f
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debugging Verilog testbench generator. Bug spotted in using renamed atom_block and clock ports
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2020-02-27 13:24:26 -07:00 |
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tangxifan
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f558405887
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ported verilog testbench generator online. Split from fabric generator. Testing to be done
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2020-02-27 12:33:09 -07:00 |
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tangxifan
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77529f4957
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adapt top Verilog testbench generation
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2020-02-26 21:30:21 -07:00 |
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tangxifan
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bb671acac3
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add formal random Verilog testbench generation
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2020-02-26 20:58:16 -07:00 |
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tangxifan
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e9adb4fdbc
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add preconfig top module Verilog generation
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2020-02-26 20:38:01 -07:00 |
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tangxifan
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b3796b0818
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build io location map
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2020-02-26 19:58:18 -07:00 |
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tangxifan
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25e0583636
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add io location map data structure and start porting verilog testbench generator
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2020-02-26 17:10:57 -07:00 |
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tangxifan
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1fa36c22d3
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Merge branch 'refactoring' into dev
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2020-02-26 11:42:50 -07:00 |
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tangxifan
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410dcf6ab6
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debugged LUT bitstream
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2020-02-26 11:42:18 -07:00 |
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tangxifan
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a26d31b87f
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make write bitstream online
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2020-02-26 11:09:23 -07:00 |
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tangxifan
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759758421d
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found the bug in physical pb mode bits and fixed
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2020-02-25 23:45:49 -07:00 |