Xifan Tang
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b941ac8a4a
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remove deprecated options
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2020-03-10 20:58:00 -06:00 |
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tangxifan
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0da6f00af5
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start reworking the openfpga tool documentation
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2020-03-10 17:29:35 -06:00 |
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tangxifan
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751735bf41
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update documentation in simulation setting syntax
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2020-03-09 17:40:33 -06:00 |
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tangxifan
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f821e60405
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clean up deadlinks in doc
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2020-03-09 10:15:16 -06:00 |
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tangxifan
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323c4fdc9a
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clean up documentation build warnings and add guidelines for port naming
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2019-12-04 11:59:10 -07:00 |
AurelienUoU
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1cf4e78502
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Update documentation and help
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2019-07-15 21:16:15 -06:00 |
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AurelienUoU
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df53f6da2c
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Updates FPGA-Verilog command lines
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2019-07-05 13:41:34 -06:00 |
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AurelienUoU
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9e99048815
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Update documentation
Merge branch 'heterogeneous' of https://github.com/LNIS-Projects/OpenFPGA into heterogeneous
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2019-07-05 11:56:02 -06:00 |
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AurelienUoU
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27dbc527a0
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Update Readme
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2019-07-05 11:06:55 -06:00 |
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AurelienUoU
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f56adc6815
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Update documentation
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2019-07-05 10:20:16 -06:00 |
BaudouinChauviere
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cb34ac0243
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Update sc_flow.rst
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2019-04-01 16:30:31 -06:00 |
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BaudouinChauviere
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361bbc13e3
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Update func_verify.rst
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2019-04-01 16:29:42 -06:00 |
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BaudouinChauviere
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a176bf3a19
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Update file_organization.rst
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2019-04-01 16:28:48 -06:00 |
Baudouin Chauviere
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39f7b0b9a2
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Update of the doc for better fit with the current version
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2019-04-01 11:55:28 -06:00 |
LNIS-Projects
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77dd7f3e04
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correction of the name of the figure
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2018-12-29 01:45:45 +01:00 |
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LNIS-Projects
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0f6ac32f43
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Further resizing
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2018-12-29 01:44:24 +01:00 |
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LNIS-Projects
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38a3b01520
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Resize the images
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2018-12-29 01:42:43 +01:00 |
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Baudouin Chauviere
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9ee50de26a
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Adding information on the layout
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2018-12-29 01:14:26 +01:00 |
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LNIS-Projects
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de7d646fa0
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Update func_verify.rst
Functional Verification documentation
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2018-12-26 18:05:24 +01:00 |
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LNIS-Projects
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c506e16d33
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Update command_line_usage.rst
Small fix
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2018-12-22 14:46:15 +01:00 |
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LNIS-Projects
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ba303450e2
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Update file_organization.rst
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2018-12-22 14:45:00 +01:00 |
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LNIS-Projects
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5fa6c84087
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New fpga_verilog commands documented
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2018-12-22 14:39:51 +01:00 |
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BaudouinChauviere
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0f87fb9c3f
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Update file_organization.rst
Correction on the routing
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2018-12-03 14:21:40 -07:00 |
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BaudouinChauviere
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e541834bd0
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Update file_organization.rst
Made similar to the SPICE one
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2018-12-03 14:20:34 -07:00 |
Aurelien Alacchi
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4a950c6857
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Flatten_hierarchy_doc
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2018-10-18 16:28:12 -06:00 |
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Aurelien Alacchi
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2cfbe2b997
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FPGA-Verilog_doc_update
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2018-10-17 16:38:03 -06:00 |
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Baudouin Chauviere
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16c0c4656e
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Adds titles and WiP tags for new parts. Tutorials included
Added title and WiP tags for comprehension and also to see what is missing and what is going to happen in the near future in the documentation
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2018-09-25 14:53:04 -06:00 |
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Xifan Tang
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fec0daa2a8
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Update a draft
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2018-09-13 22:58:54 -06:00 |
Xifan Tang
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d6d6951496
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Adding documentation
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2018-09-13 15:38:41 -06:00 |