4 Commits

Author	SHA1	Message	Date
tangxifan	477a522885	[HDL] Rename tech lib to be consistent with arch name changes	2021-03-20 18:08:03 -06:00
tangxifan	76113a80fa	[HDL] Add an adhoc yosys technology library for a heterogeneous FPGA architecture	2021-03-17 15:09:12 -06:00
tangxifan	cea43c2c45	[HDL] Add SPRAM module to generic yosys tech lib for openfpga usage	2021-03-16 18:04:31 -06:00
tangxifan	76837e02e6	[Script] Rename yosys script supporting bram and restructure techlib files	2021-03-16 16:16:53 -06:00