Commit Graph

293 Commits

Author SHA1 Message Date
tangxifan b8b846d3eb [lib] add a testcase for csv read/write for io pin table 2022-07-26 22:54:27 -07:00
tangxifan 250ebb5549 [lib] developing csv writer for io pin table 2022-07-26 22:52:13 -07:00
tangxifan e860706363 [lib] developing csv reader for pin table file 2022-07-26 21:46:44 -07:00
tangxifan 1d1c2d7e8c [lib] developing csv reader for io pin table 2022-07-26 21:08:41 -07:00
tangxifan ae328cfa7f [lib] add more apis 2022-07-26 21:01:33 -07:00
tangxifan b8bd19a234 [lib] developing io pin table data structure 2022-07-26 20:47:45 -07:00
tangxifan 5fa2df1d27 [lib] developing io pin table data structure 2022-07-26 20:31:47 -07:00
tangxifan b6ad38598d [test] add io location map reader/writer test main 2022-07-26 20:02:39 -07:00
tangxifan 0ea456c55d [lib] add io location XML reader 2022-07-26 19:58:15 -07:00
tangxifan 5b547b1c91 [lib] fixed some compilation bugs 2022-07-26 19:36:57 -07:00
tangxifan 9decccbc66 [lib] add pcf read/writers as well as a simple verilog reader 2022-07-26 16:54:23 -07:00
tangxifan 89eb2fd634 [test] add example file of io location 2022-07-26 16:34:10 -07:00
tangxifan 2ce6424dc5 [lib] add csv-parser as a single-include header 2022-07-26 16:23:48 -07:00
tangxifan 1c9da96f59 [lib] move io_location_map to libpcf 2022-07-26 16:00:28 -07:00
tangxifan 27fea8bbbe [lib] Merge librepackdc into libpcf 2022-07-26 15:54:32 -07:00
taoli4rs 59e2692b9a Update unit test data. 2022-07-22 10:45:31 -07:00
taoli4rs 0dab36f326 Fix clang issue- change string to string.c_str() for VTR_LOG. 2022-07-20 15:20:19 -07:00
taoli4rs 3762a3aae4 Code clean up based on review. 2022-07-20 14:34:44 -07:00
taoli4rs cfc0d08060 Add constrain_pin_location command in openfpga; add full flow test. 2022-07-20 11:51:00 -07:00
coolbreeze413 9fd8c02e13 header inclusions required for MinGW windows build 2022-06-29 07:03:38 +05:30
tangxifan fc7864e6a5 [FPGA-Bitstream] Clean-up bitstream distribution file format 2022-03-29 19:48:20 +08:00
tangxifan 6171abdf95 [FPGA-Bitstream] Now report_bitstream_distribution includes fabric bitstream stats 2022-03-29 19:41:15 +08:00
coolbreeze413 b728ab4ab2 fix openfpga_digest functions to work on WIN32(MinGW-w64-g++) as well as Linux 2022-03-17 22:05:30 +05:30
tangxifan 671188dfa4 [FPGA-Verilog] Now support big/little-endian in bus group 2022-02-18 23:05:03 -08:00
tangxifan 94fea84a40 [Lib] Fix a bug in memory allocation 2022-02-18 12:36:03 -08:00
tangxifan 0d620888ab [FPGA-Verilog] Now instance can output bus ports with all the pins 2022-02-18 12:03:26 -08:00
tangxifan c96f0d199d [FPGA-Verilog] Adding bus group support in Verilog testbenches 2022-02-17 23:14:28 -08:00
tangxifan e60d7d12b7 [Lib] Fixed a bug in writer 2022-02-17 17:12:07 -08:00
tangxifan 4b3f906f11 [Lib] Fixed all the syntax errors 2022-02-17 17:09:03 -08:00
tangxifan 27627bf5b4 [Lib] Add an example XML for bus group unit tests 2022-02-17 16:22:01 -08:00
tangxifan 0d7e949166 [Lib] Add unit test for bus group 2022-02-17 16:21:12 -08:00
tangxifan 76cf4e1662 [Lib] Add reader and writer for bus group 2022-02-17 16:17:37 -08:00
tangxifan 1edaa04715 [Lib] Adding XML parser for the bus group 2022-02-17 15:50:44 -08:00
tangxifan b44701bc2c [Lib] Adding the 1st version of bus group data structure 2022-02-17 15:02:37 -08:00
tangxifan a9e6b7c12e [FPGA-Bitstream] Remove version numbers when ``--no_time_stamp`` is enabled 2022-01-25 20:33:49 -08:00
tangxifan 25143d07f1 [FPGA-Bitstream] Now has a new option ``--no_time_stamp`` to all the commands that output bitstream files 2022-01-25 13:37:54 -08:00
tangxifan 4e2df9d69c [Lib] Bug fix in unintialized memory in fabric key 2021-10-10 17:59:11 -07:00
tangxifan 92eebd9abb [Lib] Upgrade fabric key writer to support the BL/WL shift register banks 2021-10-07 17:05:35 -07:00
tangxifan eddafb42c8 [Lib] Upgrade parser for fabric key to support shift register banks 2021-10-07 15:38:42 -07:00
tangxifan a15798a4e1 [Lib] Upgrade fabric key data structure to support shift register bank definitions 2021-10-07 14:42:21 -07:00
tangxifan 9693a269ee [FPGA-Bitstream] Now dont' care bits are truelly seen in single-chain and flatten QuickLogic memory bank 2021-10-07 11:31:16 -07:00
tangxifan bf473f50f8 [FPGA-Verilog] Correct bugs in logging clock frequencies 2021-10-06 11:55:57 -07:00
tangxifan fcb5470baa [Lib] Add validator to check if a clock is constrained in simulation settings 2021-10-06 11:48:23 -07:00
tangxifan 3d062872de [Lib] Upgrade openfpga arch parser to error out for unsupported configuration protocol settings 2021-10-05 14:08:01 -07:00
tangxifan 977d81679d [Engine] Upgrade check codes for WL CCFF 2021-10-01 17:23:10 -07:00
tangxifan 7b010ba0f4 [Engine] Support programming shift register clock in XML syntax 2021-10-01 11:00:38 -07:00
tangxifan 4926c323e7 [Engine] Bug fix due to the optional syntax ``num_bank`` were required in XML 2021-09-29 16:32:29 -07:00
tangxifan 834bdd2b07 [Engine] Updating fabric generator to support BL/WL shift registers. Still WIP 2021-09-28 17:29:03 -07:00
tangxifan afd03d7eb7 [Engine] Add more check codes for the CCFF circuit model used by BL/WL shift registers 2021-09-28 15:56:07 -07:00
tangxifan 0a2979d616 [Engine] Update readarchopenfpga library by adding new syntax ``num_banks`` as well as update arch writer for BL/WL protocols 2021-09-28 14:20:35 -07:00