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OpenFPGA
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2 Commits

Author SHA1 Message Date
tangxifan e10cafe0a5 Critical patch on repacking about wire LUT support. 
Previously, the wire LUT identification is too naive and does not consider all the cases
 2020-04-19 16:42:31 -06:00
tangxifan 4024ed63cb add truth table build up for physical LUTs 2020-02-25 22:39:42 -07:00