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5654 Commits

Author SHA1 Message Date
tangxifan 70b0d2e505 [doc] update pin table file format for pin direction keywords 2022-10-17 15:32:00 -07:00
tangxifan c4de6655b6 [engine] bug 2022-10-17 15:26:21 -07:00
tangxifan 609e096b1a [test] added a new test to validate explicit port direction in pin table support 2022-10-17 15:25:19 -07:00
tangxifan b82ebf2f23 [script] suppress warnings for vtr libs 2022-10-17 15:16:23 -07:00
tangxifan 0f2b8da7f0 [engine] code format 2022-10-17 14:55:34 -07:00
tangxifan 63d8b00630 [engine] syntax 2022-10-17 14:54:18 -07:00
tangxifan 811438c20e [engine] syntax 2022-10-17 14:20:23 -07:00
tangxifan 11624cd0c6 [engine] enabling new feature: pin_table_direction_convention 2022-10-17 14:08:21 -07:00
tangxifan aef94171c2 [doc] update options for pcf2place command 2022-10-17 13:55:18 -07:00
tangxifan 2f434fd4d3 [lib] developing pin dir convention support 2022-10-17 12:35:06 -07:00
tangxifan dbbabbc098 [lib] developing the support on forcing pin direction from a specific column in pin table .csv 2022-10-17 12:23:39 -07:00
tangxifan 8b00bfdff9 [test] replace hardcoded paths in task config files with relative paths 2022-10-17 11:55:57 -07:00
tangxifan aa78981e37 [test] add a new test case 'empty_pcf' to ensure 'free pin assignment' support in pcf2place; Move all the tests related to I/O constraints to a dedicated directory 2022-10-17 11:18:21 -07:00
tangxifan 18fc9071ab
Merge pull request #844 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2022-10-13 19:06:27 -07:00
github-actions[bot] 3a1c1f326a Updated Patch Count 2022-10-14 02:02:34 +00:00
tangxifan 7468daf456
Merge pull request #842 from lnis-uofu/rst_on_lut_strong 
Strong test case to validate that repacker can handle reset signal on LUTs
 2022-10-13 18:59:43 -07:00
tangxifan 6611fba9d5 Merge branch 'rst_on_lut_strong' of https://github.com/lnis-uofu/OpenFPGA into rst_on_lut_strong 2022-10-13 16:28:22 -07:00
tangxifan 0af6c76239 [engine] code format 2022-10-13 16:27:57 -07:00
tangxifan d1f3338837 [engine] now repacker find only routable pins when given a net to search routing traces 2022-10-13 16:26:45 -07:00
tangxifan e9ee039e60
Merge branch 'master' into rst_on_lut_strong 2022-10-13 16:01:57 -07:00
tangxifan 33e2b16cb1 [arch] fixed a bug which caused verification failed 2022-10-13 15:33:43 -07:00
tangxifan 31da9bf6ea [engine] now repack can find a routing trace from the port in the same type at top-level pb_graph_node 2022-10-13 15:10:25 -07:00
tangxifan 1c36ac28f1 [arch] code format 2022-10-13 12:17:32 -07:00
tangxifan 32f48f16c7 [arch] fixed a few bugs 2022-10-13 11:54:58 -07:00
tangxifan b0be27b384 [test] add repack design constraints files 2022-10-13 11:22:48 -07:00
tangxifan 5cf315958d [test] deploy new test to basic regression tests 2022-10-13 11:17:34 -07:00
tangxifan 7b7217d116 [arch]add new arch to test 2022-10-13 11:08:51 -07:00
tangxifan 7f67794787 [arch]add new arch to test 2022-10-13 10:54:40 -07:00
tangxifan 07441a978c
Merge pull request #841 from mustafaarslan0/patch-1 
Fixed the typo of OpenFPGA Architecture files which have fracturable DSP
 2022-10-13 10:09:30 -07:00
mustafa.arslan d7a253408d
Update k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml 
Mode port assertions should be bind with "physical_mode_port_rotate_offset" instead of "physical_mode_pin_rotate_offset".
 2022-10-13 14:00:59 +03:00
mustafa.arslan 6f55371d4b
Update k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml 
Mode port assertions should be bind with "physical_mode_port_rotate_offset" instead of "physical_mode_pin_rotate_offset".
 2022-10-13 13:53:32 +03:00
tangxifan c4d9c17bc4
Merge pull request #838 from lnis-uofu/dependabot/submodules/yosys-plugins-b3430d2 
Bump yosys-plugins from `27208ce` to `b3430d2`
 2022-10-12 18:00:14 -07:00
tangxifan a9e45be8cc
Merge pull request #839 from yunuseryilmaz18/patch-2 
Update frac_mem_32k.v
 2022-10-12 17:59:58 -07:00
Yunus Emre ERYILMAZ f62d435b1e
Update frac_mem_32k.v 2022-10-12 09:35:35 +03:00
dependabot[bot] c45b51a319
Bump yosys-plugins from `27208ce` to `b3430d2` 
Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `27208ce` to `b3430d2`.
- [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases)
- [Commits](27208ce082...b3430d2e55)

---
updated-dependencies:
- dependency-name: yosys-plugins
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2022-10-12 06:19:46 +00:00
tangxifan d79ada8720
Merge pull request #837 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2022-10-07 17:07:08 -07:00
github-actions[bot] 3ffcfb54c9 Updated Patch Count 2022-10-08 00:04:52 +00:00
tangxifan 215d9dfccb
Merge pull request #836 from lnis-uofu/xmllint 
Format architecture XML files
 2022-10-07 13:36:53 -07:00
tangxifan 35869b480a
Merge branch 'master' into xmllint 2022-10-07 10:47:43 -07:00
tangxifan 6e2040f678
Merge pull request #835 from mustafaarslan0/patch-1 
Update k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
 2022-10-07 10:44:15 -07:00
tangxifan 1abdb56609 [script] make xmllint indent specific to two space 2022-10-07 10:33:59 -07:00
tangxifan 85089cbc88 [arch] apply xml format for all the architecture files 2022-10-07 10:31:51 -07:00
tangxifan d6dd540541 [script] enable inplace for xml formatting 2022-10-07 10:28:47 -07:00
tangxifan 5e220048ab [ci] add XML lint to dependency; enable xml format in CI 2022-10-07 10:21:14 -07:00
tangxifan 6c12e8dc24 [script] developing xml formatting command 2022-10-07 10:16:00 -07:00
tangxifan 4d4ab60fe4 [ci] rename workflow 2022-10-07 10:12:40 -07:00
mustafa.arslan 508c01cef6
Update k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml 
Mode port assertions should be bind with "physical_mode_port_rotate_offset" instead of "physical_mode_pin_rotate_offset".
 2022-10-07 09:38:07 +03:00
tangxifan ae708c987f
Merge pull request #834 from lnis-uofu/code_format 
Now C/C++ codes follow a clang format
 2022-10-06 22:35:19 -07:00
tangxifan 6de0cb86b3 [ci] bug fix 2022-10-06 20:49:38 -07:00
tangxifan df106d9bef [ci] added a workflow to check code format 2022-10-06 19:21:25 -07:00