tangxifan
|
78d4991a4e
|
[script] add missing flags required
|
2022-12-01 14:49:05 -08:00 |
tangxifan
|
33b400de39
|
[script] compilation passed but failed when loading .so to tclsh
|
2022-12-01 13:51:50 -08:00 |
tangxifan
|
819b716260
|
[script] debugging
|
2022-12-01 12:30:57 -08:00 |
tangxifan
|
2e585024f7
|
[script] debugging
|
2022-12-01 12:26:30 -08:00 |
tangxifan
|
48a9a97562
|
[script] enabling swig in cmake compilation
|
2022-12-01 12:23:01 -08:00 |
tangxifan
|
0574efa9b3
|
[script] reworking cmakefile for swig integration
|
2022-12-01 12:06:27 -08:00 |
tangxifan
|
10d52f1f8b
|
[engine] add swig interface file
|
2022-12-01 11:54:59 -08:00 |
tangxifan
|
74b32c3a5c
|
[script] enable shared library for openfpga
|
2022-12-01 11:42:25 -08:00 |
tangxifan
|
f1a317b384
|
[engine] format
|
2022-11-24 21:04:04 -08:00 |
tangxifan
|
24a174c7a4
|
[engine] fixed syntax errors
|
2022-11-23 17:06:27 -08:00 |
tangxifan
|
07424b1e7f
|
[engine] now main() is encapuslated in a class OpenfpgaShell
|
2022-11-23 16:52:22 -08:00 |
tangxifan
|
c4de6655b6
|
[engine] bug
|
2022-10-17 15:26:21 -07:00 |
tangxifan
|
0f2b8da7f0
|
[engine] code format
|
2022-10-17 14:55:34 -07:00 |
tangxifan
|
63d8b00630
|
[engine] syntax
|
2022-10-17 14:54:18 -07:00 |
tangxifan
|
11624cd0c6
|
[engine] enabling new feature: pin_table_direction_convention
|
2022-10-17 14:08:21 -07:00 |
tangxifan
|
0af6c76239
|
[engine] code format
|
2022-10-13 16:27:57 -07:00 |
tangxifan
|
d1f3338837
|
[engine] now repacker find only routable pins when given a net to search routing traces
|
2022-10-13 16:26:45 -07:00 |
tangxifan
|
31da9bf6ea
|
[engine] now repack can find a routing trace from the port in the same type at top-level pb_graph_node
|
2022-10-13 15:10:25 -07:00 |
tangxifan
|
afdc071c4c
|
[engine] apply code format
|
2022-10-06 18:13:33 -07:00 |
tangxifan
|
e2debd2dde
|
[engine] add missing header files after coding formatter sorts the include files
|
2022-10-06 18:08:57 -07:00 |
tangxifan
|
6d31b319a2
|
[engine] update source files subject to code formatting rules
|
2022-10-06 17:08:50 -07:00 |
tangxifan
|
0d8d8446ee
|
[test] fixed a bug where OPIN for direct connection is included in GSB
|
2022-09-30 15:24:51 -07:00 |
tangxifan
|
fb2693171b
|
[engine] fixed a bug which causes errors in repacker
|
2022-09-28 16:30:11 -07:00 |
tangxifan
|
36b3e64b35
|
[engine] now pb_fixup can also accept vtr's post-routing-clustering sync up results
|
2022-09-28 12:17:16 -07:00 |
tangxifan
|
3285af4107
|
[engine] syntax
|
2022-09-28 11:39:37 -07:00 |
tangxifan
|
51f54bbf20
|
[engine] developing the steps to annotate clustering results
|
2022-09-27 16:54:48 -07:00 |
tangxifan
|
8272d2dcbc
|
[engine] enrich verbose output for repacker, easier to debug
|
2022-09-27 10:46:57 -07:00 |
tangxifan
|
e19ca1c6d1
|
[engine] fixed a bug when decoding bitstream for connnection blocks: now use incoming edges from gsb
|
2022-09-19 18:49:54 -07:00 |
tangxifan
|
c922259c23
|
[engine] remove warnings and update vtr
|
2022-09-19 14:53:30 -07:00 |
tangxifan
|
90ddd2ce32
|
[engine] now get incoming edges for IPINs only from GSB
|
2022-09-19 14:02:13 -07:00 |
tangxifan
|
3c6ef1925c
|
[engine] now sort ipin incoming edges
|
2022-09-19 11:00:08 -07:00 |
tangxifan
|
373566416c
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
|
2022-09-16 16:47:21 -07:00 |
tangxifan
|
f0fe781dbc
|
[engine] fixed a bug
|
2022-09-16 10:45:27 -07:00 |
tangxifan
|
bba5b7b070
|
[engine] syntax
|
2022-09-15 23:04:37 -07:00 |
tangxifan
|
cbc71c75c4
|
[engine] now io indexing follows a natural way
|
2022-09-15 23:01:35 -07:00 |
tangxifan
|
8378ad4bf3
|
[engine] fixed a bug on mistakenly adding I/O child modules for direct connections
|
2022-09-14 17:13:23 -07:00 |
tangxifan
|
036933dc14
|
[engine] fixed more bugs due to the extra modules added to top-level module when using memory bank or frame-based protocols
|
2022-09-14 16:46:10 -07:00 |
tangxifan
|
0425b00af5
|
[engine] fixed a bug for frame-based protocols
|
2022-09-14 16:41:30 -07:00 |
tangxifan
|
cb89488f76
|
[engine] now support a custom list for indexing I/O children in each module
|
2022-09-14 15:54:55 -07:00 |
tangxifan
|
eb8b7e6901
|
[engine] fixed a bug in i/o indexing
|
2022-09-14 11:30:34 -07:00 |
tangxifan
|
1c2192a87d
|
[engine] fixed a few bugs
|
2022-09-12 16:50:32 -07:00 |
tangxifan
|
2fc124e109
|
[engine] now repack has a new option "--ignore_global_nets_on_pins"
|
2022-09-12 16:18:26 -07:00 |
tangxifan
|
e5c7a3df9f
|
[engine] syntax
|
2022-09-07 15:51:54 -07:00 |
tangxifan
|
56619f9a47
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
|
2022-09-07 15:04:05 -07:00 |
tangxifan
|
8d09773e65
|
[engine] remove unnecessary checks from sb mirror checker
|
2022-09-07 11:55:08 +08:00 |
tangxifan
|
e748c7697d
|
[engine] update code comments
|
2022-09-06 13:51:29 -07:00 |
tangxifan
|
eab3580f79
|
[engine] now consider circuit model rather than switchId and SegmentId when identifying GSB structure similarity
|
2022-09-06 13:40:29 -07:00 |
tangxifan
|
59440082ed
|
[engine] fixed some syntax errors
|
2022-09-06 11:55:40 -07:00 |
tangxifan
|
2f84ce5955
|
[engine] now move rr_gsb mirror function outside the class, because of the circuit_lib should be used
|
2022-09-06 11:48:21 -07:00 |
tangxifan
|
b26b2d0ed0
|
Merge branch 'master' into vtr_upgrade
|
2022-09-02 10:05:23 -07:00 |
coolbreeze413
|
04abd1a36f
|
add <array> declaration to fix gcc error
|
2022-09-02 19:26:28 +05:30 |
tangxifan
|
9e1abf5898
|
Merge branch 'master' into vtr_upgrade
|
2022-09-01 21:39:14 -07:00 |
tangxifan
|
d3f08a893c
|
[engine] now frame view will not build nets for configuration bus
|
2022-09-01 20:02:00 -07:00 |
tangxifan
|
001367ea41
|
[engine] syntax
|
2022-09-01 16:40:17 -07:00 |
tangxifan
|
1f5e4d4215
|
[engine] update fabric bitstream implementation
|
2022-09-01 16:29:42 -07:00 |
tangxifan
|
ea6f609181
|
[engine] fixing a bug in fabric bitstream encoding
|
2022-09-01 16:28:17 -07:00 |
tangxifan
|
e4aa6e0ee5
|
[engine] syntax
|
2022-09-01 15:17:39 -07:00 |
tangxifan
|
ee87b5c348
|
[engine] fixed all the remaining syntax errors due to API mismatches
|
2022-09-01 09:57:12 -07:00 |
tangxifan
|
7c5046cf4e
|
[engine] include the correct header file
|
2022-09-01 09:23:05 -07:00 |
tangxifan
|
71ad0721a1
|
Merge branch 'master' into vtr_upgrade
|
2022-08-31 13:56:17 -07:00 |
tangxifan
|
26388dfb2f
|
[engine] fixed a bug which causes errors when writing unique GSB to files
|
2022-08-30 15:45:00 -07:00 |
tangxifan
|
3656154913
|
[engine] fixed syntax errors
|
2022-08-29 21:17:48 -07:00 |
tangxifan
|
2321ea6274
|
[engine] complete the code required to output rr_gsb with options
|
2022-08-29 20:44:16 -07:00 |
tangxifan
|
12a30196e0
|
[engine] updating gsb writer; Unfinished!!!
|
2022-08-29 16:58:48 -07:00 |
tangxifan
|
b9abdbc5d4
|
[engine] enable verbose output
|
2022-08-27 19:59:57 -07:00 |
tangxifan
|
e9d6e7e38a
|
[engine] update vtr and enable more debugging info
|
2022-08-27 19:12:43 -07:00 |
tangxifan
|
0c2b49ddb9
|
[engine] remove debugging log output
|
2022-08-27 13:06:05 -07:00 |
tangxifan
|
25f6c529e0
|
[engine] fixed syntax errors when using clang
|
2022-08-25 09:58:43 -07:00 |
tangxifan
|
b432ac05b4
|
[script] fixed typo on IPO options
|
2022-08-24 21:51:29 -07:00 |
tangxifan
|
f853040875
|
[script] enable IPO in cmakefile
|
2022-08-24 14:34:33 -07:00 |
tangxifan
|
ba6ae05091
|
[engine] update vtr and add in_edge checks to link_arch
|
2022-08-24 12:22:20 -07:00 |
tangxifan
|
d1edc51165
|
[engine] clean up header files that include rr_graph_obj
|
2022-08-23 18:38:21 -07:00 |
tangxifan
|
b3e4a06969
|
[engine] adapt vpr wrapper to the latest main.cpp from vtr
|
2022-08-23 14:28:05 -07:00 |
tangxifan
|
892770a8fb
|
[engine] debugging subtile index failures
|
2022-08-23 14:13:10 -07:00 |
tangxifan
|
0a6b794ef0
|
[engine] fixed bugs in subtiles. Revisited the usage of client functions
|
2022-08-23 12:35:04 -07:00 |
tangxifan
|
019e663e12
|
[engine] fixing the bugs on building global nets to sub tile pins
|
2022-08-23 11:58:44 -07:00 |
tangxifan
|
10cefebca8
|
[engine] fixing bugs on using subtile index
|
2022-08-23 11:00:23 -07:00 |
tangxifan
|
ba0ddd01d3
|
[engine] fixing the bugs on subtiles
|
2022-08-23 10:52:05 -07:00 |
tangxifan
|
c17e5d46ab
|
[engine] fixed a bug due to the API of subtile data structure
|
2022-08-22 21:44:05 -07:00 |
tangxifan
|
5d6a90d983
|
[engine] remove compile warnings
|
2022-08-22 20:59:50 -07:00 |
tangxifan
|
800ce6a290
|
[engine] avoid function naming conflicts
|
2022-08-18 19:33:56 -07:00 |
tangxifan
|
903dd6cef6
|
[engine] remove warnings
|
2022-08-18 15:56:18 -07:00 |
tangxifan
|
a52597361b
|
[script] remove duplicated libraries in dependency list for some libopenfpga
|
2022-08-18 11:34:01 -07:00 |
tangxifan
|
e9c4d102c1
|
[engine] rename files to avoid conflicts with VPR files
|
2022-08-17 20:01:50 -07:00 |
tangxifan
|
40100c1ba3
|
[engine] remove warnings
|
2022-08-17 19:07:49 -07:00 |
tangxifan
|
cb4b106d4e
|
[engine] correcting syntax errors
|
2022-08-17 16:36:14 -07:00 |
tangxifan
|
dfe30df462
|
[engine] resolve compilation warnings
|
2022-08-17 16:32:21 -07:00 |
tangxifan
|
e0ae851e28
|
[engine] correcting compilation errors due to vpr upgrade
|
2022-08-17 16:25:12 -07:00 |
tangxifan
|
ce32c3b30b
|
[engine] fixing api errors
|
2022-08-17 14:47:14 -07:00 |
tangxifan
|
3c2bf5159b
|
[engine] use new API to get node side
|
2022-08-17 14:38:40 -07:00 |
tangxifan
|
3c12810ad9
|
[engine] debugging
|
2022-08-17 14:37:13 -07:00 |
tangxifan
|
8f1aac885e
|
[engine] fixing mismatches in APIs
|
2022-08-17 14:19:02 -07:00 |
tangxifan
|
4e871be357
|
[engine] adapt the use of API in RRGraph for annotation functions
|
2022-08-17 10:50:16 -07:00 |
tangxifan
|
01d53db484
|
[script] Adapt timing analysis APIs
|
2022-08-17 10:28:58 -07:00 |
tangxifan
|
ade8f43a36
|
[engine] Updating RRGraph Annotation and VTr
|
2022-08-17 10:16:55 -07:00 |
tangxifan
|
716929536d
|
[engine] adapting source files for new APIs in VTR
|
2022-08-17 09:54:31 -07:00 |
tangxifan
|
d3d81f0b18
|
[engine] keep adapting to latest VTR
|
2022-08-16 21:05:50 -07:00 |
tangxifan
|
0c329866da
|
[engine] Use RRGraphView in openfpga source codes
|
2022-08-16 16:48:32 -07:00 |
tangxifan
|
ce7204daec
|
[engine] debugging
|
2022-08-16 16:35:08 -07:00 |
tangxifan
|
c1256ae818
|
[engine] added command 'pcf2place' to openfpga
|
2022-07-28 11:30:36 -07:00 |
tangxifan
|
2a5bffa6b9
|
[engine] developing pcf2place integration to openfpga
|
2022-07-28 10:30:43 -07:00 |
tangxifan
|
1c9da96f59
|
[lib] move io_location_map to libpcf
|
2022-07-26 16:00:28 -07:00 |
tangxifan
|
27fea8bbbe
|
[lib] Merge librepackdc into libpcf
|
2022-07-26 15:54:32 -07:00 |
tangxifan
|
23f98d6a3b
|
[engine] fixed a few bugs
|
2022-07-26 13:55:29 -07:00 |
tangxifan
|
85bcb36f34
|
[engine] fix compiler errors
|
2022-07-26 12:25:40 -07:00 |
tangxifan
|
0862eceed0
|
[engine] add an XML write to io location map: In the long run, we should decouple the writer function from the data structure!!!
|
2022-07-26 12:17:45 -07:00 |
taoli4rs
|
3762a3aae4
|
Code clean up based on review.
|
2022-07-20 14:34:44 -07:00 |
taoli4rs
|
cfc0d08060
|
Add constrain_pin_location command in openfpga; add full flow test.
|
2022-07-20 11:51:00 -07:00 |
tangxifan
|
a7e87b9432
|
[FPGA-Bitstream] note limitations
|
2022-05-25 18:38:01 +08:00 |
tangxifan
|
ffac5a66e1
|
[FPGA-Bitstream] Now encode address bits to save memory in bitstream database
|
2022-05-25 17:45:08 +08:00 |
tangxifan
|
bf1a81fbb5
|
[FPGA-bitstream] add timer to computing intensive functions
|
2022-05-25 14:52:32 +08:00 |
tangxifan
|
a20f6eaf06
|
[Engine] Fixed a few bugs
|
2022-04-10 21:29:38 +08:00 |
tangxifan
|
755be78b39
|
[Engine] Now GSB output file contains segments name and pin name in SB module
|
2022-04-10 21:22:30 +08:00 |
tangxifan
|
6171abdf95
|
[FPGA-Bitstream] Now report_bitstream_distribution includes fabric bitstream stats
|
2022-03-29 19:41:15 +08:00 |
tangxifan
|
4d67864c2c
|
[Engine] Now global port can be connected partial pins of a tile port
|
2022-03-20 11:36:03 +08:00 |
tangxifan
|
8ab090651a
|
[FPGA-Verilog] Now port/wire names uses "__" to avoid collision with FPGA global ports
|
2022-03-16 20:51:37 +08:00 |
tangxifan
|
235887e03a
|
[FPGA-Verilog] Fixed a bug on config-enable signals
|
2022-02-23 22:35:23 -08:00 |
tangxifan
|
086642d134
|
[FPGA-Verilog] Now preconfigured wrapper can handle config_enable signals correctly
|
2022-02-23 15:33:24 -08:00 |
tangxifan
|
1c18d14ad5
|
[FPGA-Verilog] Add big/little endian support to output ports
|
2022-02-19 09:23:48 -08:00 |
tangxifan
|
3e43a60fdc
|
[FPGA-Verilog] Add big/little endian support when instanciate reference benchmarks
|
2022-02-19 09:15:38 -08:00 |
tangxifan
|
671188dfa4
|
[FPGA-Verilog] Now support big/little-endian in bus group
|
2022-02-18 23:05:03 -08:00 |
tangxifan
|
790715f46a
|
[FPGA-Verilog] Fixing bugs when using bus group in full testbench generator
|
2022-02-18 15:41:35 -08:00 |
tangxifan
|
401f673f16
|
[FPGA-Verilog] Streamline codes by using APIs
|
2022-02-18 14:47:36 -08:00 |
tangxifan
|
c16ea8d082
|
[FPGA-Verilog] Fixing bugs in naming wires in verilog testbenches
|
2022-02-18 14:34:32 -08:00 |
tangxifan
|
a4dc86a33d
|
[FPGA-Verilog] Now output atom block name removal has a dedicated function
|
2022-02-18 14:30:46 -08:00 |
tangxifan
|
f5dd89bbd9
|
[FPGA-Verilog] Fixed bugs in preconfigured wrapper generator when bus group is used
|
2022-02-18 14:08:03 -08:00 |
tangxifan
|
0d620888ab
|
[FPGA-Verilog] Now instance can output bus ports with all the pins
|
2022-02-18 12:03:26 -08:00 |
tangxifan
|
aa375fd7a4
|
[FPGA-Verilog] Fixed a bug due to the use of bus group in testbench generator
|
2022-02-18 11:31:11 -08:00 |
tangxifan
|
6da0ede9b0
|
[FPGA-Verilog] Adding bus group support to all Verilog testbench generators
|
2022-02-17 23:48:44 -08:00 |
tangxifan
|
c96f0d199d
|
[FPGA-Verilog] Adding bus group support in Verilog testbenches
|
2022-02-17 23:14:28 -08:00 |
tangxifan
|
38601f325b
|
[Engine] Add bus group to OpenFPGA core
|
2022-02-17 17:28:55 -08:00 |
tangxifan
|
e67f8ad8b2
|
[FPGA-Verilog] Now full testbench does not check any output vectors during configuration phase
|
2022-02-15 17:19:50 -08:00 |
tangxifan
|
be8f18310d
|
[FPGA-Verilog] Fix a bug on the polarity of reset signals that drive FPGA instances
|
2022-02-14 17:16:26 -08:00 |
tangxifan
|
d3f68db228
|
[FPGA-Verilog] fixing bugs in reset ports for counters in full testbenches
|
2022-02-14 17:00:54 -08:00 |
tangxifan
|
34e192c5ca
|
[FPGA-Verilog] Fixed a bug on wiring FPGA global ports
|
2022-02-14 15:21:29 -08:00 |
tangxifan
|
8d48492ec0
|
[FPGA-Verilog] Add clock ports to the white list when adding postfix
|
2022-02-14 11:09:00 -08:00 |
tangxifan
|
5794561f7b
|
[FPGA-Verilog] Now shared input wire/register has a postfix in full testbench
|
2022-02-14 10:39:27 -08:00 |
tangxifan
|
2ca73d79e4
|
[FPGA-Verilog] Fixed the bug on pin constraints
|
2022-02-13 22:08:06 -08:00 |
tangxifan
|
b1377f0d34
|
[FPGA-Verilog] Fix syntax errors
|
2022-02-13 20:29:05 -08:00 |
tangxifan
|
6e132aace4
|
[FPGA-Verilog] Remove the prefix added by VPR in preconfigured top module
|
2022-02-13 20:26:21 -08:00 |
tangxifan
|
fb4106de19
|
[FPGA-Verilog] Fixed a bug in naming mismatch
|
2022-02-13 20:06:35 -08:00 |
tangxifan
|
a068237082
|
[FPGA-Verilog] Rename internal wire names in testbenches, in order to be consistent with reference benchmarks
|
2022-02-13 19:55:16 -08:00 |
tangxifan
|
1c94d0f285
|
[FPGA-Verilog] Now preconfig testbench generator has a new option ``--use_relative_path``
|
2022-02-01 13:25:09 -08:00 |
tangxifan
|
f311a034bb
|
[FPGA-Verilog] Now full testbench generator has a new option ``--use_relative_path``
|
2022-02-01 12:17:02 -08:00 |
tangxifan
|
2b8e2de0c9
|
[FPGA-Verilog] Fix bugs
|
2022-01-31 14:23:04 -08:00 |
tangxifan
|
6c29c286bc
|
[FPGA-Verilog] Fix a bug which cause errors
|
2022-01-31 14:06:58 -08:00 |
tangxifan
|
63f44adf15
|
[FPGA-Verilog] Now have a new option ``--use_relative_path``
|
2022-01-31 12:48:05 -08:00 |
Emin Cetin
|
6c2c4e8b14
|
adding comment
|
2022-01-28 08:57:45 +03:00 |
Emin Cetin
|
f9b47c3b34
|
missing semicolon
|
2022-01-27 16:49:04 +03:00 |
Emin Cetin
|
8f7ee4e338
|
changing condition of bitstream downloading
|
2022-01-27 11:49:55 +03:00 |
tangxifan
|
a9a56686e2
|
[Engine] Add a new option ``--unique`` to command ``write_gsb_to_xml``
|
2022-01-26 11:10:29 -08:00 |
tangxifan
|
a9e6b7c12e
|
[FPGA-Bitstream] Remove version numbers when ``--no_time_stamp`` is enabled
|
2022-01-25 20:33:49 -08:00 |
tangxifan
|
33064ca4cf
|
[FPGA-SDC] Add a new option ``--no_time_stamp`` to all the commands
|
2022-01-25 15:51:28 -08:00 |
tangxifan
|
b09e13b42c
|
[FPGA-Verilog] Fixed a bug on invalid option of a command
|
2022-01-25 13:45:44 -08:00 |
tangxifan
|
25143d07f1
|
[FPGA-Bitstream] Now has a new option ``--no_time_stamp`` to all the commands that output bitstream files
|
2022-01-25 13:37:54 -08:00 |
tangxifan
|
62b57b05d2
|
[Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp``
|
2022-01-25 12:09:08 -08:00 |
nadeemyaseen-rs
|
dbe8616837
|
Merge remote-tracking branch 'upstream/master' into update_from_upstream
|
2021-12-23 00:00:22 +05:00 |
Tarachand Pagarani
|
02e4ae9740
|
allow bitstream setting on hard blocks
|
2021-12-07 03:42:22 -08:00 |
tangxifan
|
ff264c00a2
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
|
2021-10-31 11:51:34 -07:00 |
tangxifan
|
91627abe12
|
[FPGA-Verilog] Fixed a bug on the non-inverted reset signal in testbenches when pin constraints are provided
|
2021-10-30 11:53:46 -07:00 |
tangxifan
|
6586ea7816
|
[Engine] Bug fix for fabric key writer which errors out when there is no BL/WL banks in the architecture
|
2021-10-11 09:40:02 -07:00 |
tangxifan
|
546350ae41
|
[FPGA-Verilog] Revert back to the previous precomputing strategy for shift register clocks
|
2021-10-10 23:19:39 -07:00 |
tangxifan
|
b9c540ec3f
|
[Engine] Upgrade fabric key writer to support BL/WL shift register banks
|
2021-10-10 21:14:14 -07:00 |
tangxifan
|
202b50c0e3
|
[FPGA-Verilog] Fixed a weird bug which causes totally different results in fixed and auto shift register clock freq; However, this is a dirty fix. Require further study to know why
|
2021-10-10 20:57:23 -07:00 |
tangxifan
|
de3275e9ba
|
[FPGA-Verilog] Fixed a critical in verilog testbench which caused the last bit of bitstream skipped when loading to shift register chains
|
2021-10-10 16:56:07 -07:00 |
tangxifan
|
1c46a92559
|
[FPGA-Bitstream] Bug fix
|
2021-10-09 21:59:56 -07:00 |
tangxifan
|
6aa4991314
|
[FPGA-Verilog] Bug fix
|
2021-10-09 21:34:07 -07:00 |
tangxifan
|
7810f376c8
|
[FPGA-Bitstream] Patch code comments
|
2021-10-09 21:03:01 -07:00 |
tangxifan
|
34575f7222
|
[FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank
|
2021-10-09 20:39:45 -07:00 |
tangxifan
|
aac74d9163
|
[Engine] Bug fix
|
2021-10-09 18:46:20 -07:00 |
tangxifan
|
fa08f44107
|
[Engine] Bug fix
|
2021-10-09 16:58:56 -07:00 |
tangxifan
|
19a551e641
|
[Engine] Upgrade fabric generator to support multiple shift register banks in a configuration region
|
2021-10-09 16:44:04 -07:00 |
tangxifan
|
932beb480a
|
[Engine] Add fast look-up to the shift register bank data structure
|
2021-10-08 22:00:01 -07:00 |
tangxifan
|
e3ff40d9e0
|
[Engine] Add missing return value
|
2021-10-08 20:17:55 -07:00 |
tangxifan
|
39a69e0d88
|
[Engine] Upgrading fabric generator to support customizable shift register banks from fabric key and configuration protocols
|
2021-10-08 17:58:06 -07:00 |
tangxifan
|
8f5f30792f
|
[Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface
|
2021-10-08 15:25:37 -07:00 |
tangxifan
|
f7484d4323
|
[Engine] Update the key memory data structure to contain shift register bank general information
|
2021-10-08 10:42:18 -07:00 |
tangxifan
|
9693a269ee
|
[FPGA-Bitstream] Now dont' care bits are truelly seen in single-chain and flatten QuickLogic memory bank
|
2021-10-07 11:31:16 -07:00 |
tangxifan
|
54a8809b3c
|
[FPGA-Verilog] Bug fix in computing clock frequency for shift register chains
|
2021-10-06 16:49:28 -07:00 |
tangxifan
|
27153bbc89
|
[FPGA-Verilog] Bug fix in matching shift register clocks between verilog ports and simulation setting definition
|
2021-10-06 13:38:51 -07:00 |
tangxifan
|
bf473f50f8
|
[FPGA-Verilog] Correct bugs in logging clock frequencies
|
2021-10-06 11:55:57 -07:00 |
tangxifan
|
fcb5470baa
|
[Lib] Add validator to check if a clock is constrained in simulation settings
|
2021-10-06 11:48:23 -07:00 |
tangxifan
|
82ed6b177b
|
[FPGA-Verilog] Now consider clock constraints for BL/WL shift registers
|
2021-10-06 11:39:28 -07:00 |
tangxifan
|
2ea9826b17
|
[FPGA-Bitstream] Bug fix in wrong option name
|
2021-10-05 18:58:47 -07:00 |
tangxifan
|
ad54c8547e
|
[FPGA-Bitstream] Added an option to ``write_fabric_bitstream`` command to enable outputting don't care bits in bitstream files
|
2021-10-05 18:54:02 -07:00 |
tangxifan
|
fdd75c4ec8
|
[FPGA-Bitstream] Enable don't care bit to be outputted in bitstream file for QuickLogic memory banks
|
2021-10-05 17:54:07 -07:00 |
tangxifan
|
3efd6840a8
|
[Engine] Bug fix for missing WLR ports in auto-generated shift register banks
|
2021-10-04 16:58:01 -07:00 |
tangxifan
|
06b018cfe7
|
[FPGA-Bitstream] Reverse bitstream for shift register due to its FIFO nature
|
2021-10-03 16:05:33 -07:00 |
tangxifan
|
2badcb58f2
|
[FPGA-Verilog] Fixed a critical bug in verilog testbench generator for QL memory bank using BL/WL register which causes misalignment in shift register loading
|
2021-10-03 16:04:47 -07:00 |
tangxifan
|
28904ff526
|
[Engine] Bug fix on wrong port type for shift register chains
|
2021-10-03 12:31:58 -07:00 |
tangxifan
|
756b4c7dc8
|
[FPGA-Verilog] Bug fix in estimating the simulation period for QuickLogic memory bank using BL/WL shift registers
|
2021-10-03 12:11:20 -07:00 |
tangxifan
|
3eb601531a
|
[FPGA-Verilog] Many bug fixes
|
2021-10-02 23:39:53 -07:00 |
tangxifan
|
d453e6477d
|
[FPGA-Verilog] Bug fix
|
2021-10-02 22:32:57 -07:00 |
tangxifan
|
02af633acd
|
[FPGA-Verilog] Fixed several bugs in testbench generator which caused iVerilog errors
|
2021-10-02 22:14:15 -07:00 |
tangxifan
|
fa7e168137
|
[FPGA-Verilog] Now testbench generator connects global shift register clocks to FPGA ports
|
2021-10-02 22:08:14 -07:00 |
tangxifan
|
76d58ebaa0
|
[FPGA-Verilog] Move clock generator to generic stimuli and shift register clock period is auto tuned by programming clock period
|
2021-10-02 21:48:10 -07:00 |
tangxifan
|
54ec74d8d2
|
[FPGA-Verilog] Bug fix in code generator
|
2021-10-02 17:31:37 -07:00 |
tangxifan
|
32fc0a1692
|
[FPGA-Verilog] Upgrading verilog testbench generator for QuickLogic memory bank using BL/WL shift register
|
2021-10-02 17:25:27 -07:00 |
tangxifan
|
f686dd1f60
|
[FPGA-Bitstream] Do not reverse for now. Previous solution looks correct
|
2021-10-01 23:12:38 -07:00 |
tangxifan
|
198517a898
|
[FPGA-Bitstream] Bug fix on bitstream sequence for QuickLogic memory bank using shift registers
|
2021-10-01 19:59:50 -07:00 |
tangxifan
|
2de6be44d6
|
[Engine] Fixed a critical bug which causes bitstream wrong for QuickLogic memory bank when fast configuration is enabled
|
2021-10-01 18:27:42 -07:00 |
tangxifan
|
477c1cd062
|
[Engine] Fixed a critical bug which causes undriven BL/WLs between shift register banks and child modules at the top-level module
|
2021-10-01 17:38:26 -07:00 |
tangxifan
|
977d81679d
|
[Engine] Upgrade check codes for WL CCFF
|
2021-10-01 17:23:10 -07:00 |
tangxifan
|
9e5debabe1
|
[FPGA-Bitstream] Enable fast configuration for QuickLogic memory banks
|
2021-10-01 16:23:38 -07:00 |
tangxifan
|
4f7ab01bf5
|
[FPGA-Bitstream] Reworked the bitstream writer to dump BL/WL words separately
|
2021-10-01 15:47:13 -07:00 |
tangxifan
|
2bd2788e77
|
[Engine] Upgrading testbench generator to support QuickLogic memory bank with shift registers
|
2021-10-01 11:23:40 -07:00 |
tangxifan
|
cf96d9ff01
|
[Engine] Add programming shift register clock to internal global port data structure
|
2021-10-01 11:05:31 -07:00 |
tangxifan
|
7b010ba0f4
|
[Engine] Support programming shift register clock in XML syntax
|
2021-10-01 11:00:38 -07:00 |
tangxifan
|
96828e456a
|
[FPGA-Bitstream] Fixed a critical bug which cause reshaping bitstream wrong
|
2021-09-30 22:07:46 -07:00 |
tangxifan
|
4bdff1554d
|
[Engine] Fixed a critical bug which cause BL/WL sharing in shift-register-based memory bank broken
|
2021-09-30 21:20:56 -07:00 |
tangxifan
|
33972fc0ec
|
[FPGA-Bitstream] Upgraded bitstream writer to support QuickLogic memory bank using shift registers
|
2021-09-30 21:05:41 -07:00 |
tangxifan
|
4526133089
|
[FPGA-Bitstream] Add a new data structure that stores fabric bitstream for memory bank using shift registers
|
2021-09-30 17:01:02 -07:00 |
tangxifan
|
43c569b612
|
[FPGA-Bitstream] Encapusulate the data structur storing memory bank fabric bitstream for flatten BL/WL into an object
|
2021-09-30 14:47:21 -07:00 |
tangxifan
|
4d8019b7c1
|
[FPGA-Bitstream] Bug fix in bitstream generator for shift-register-based memory bank
|
2021-09-29 22:32:45 -07:00 |
tangxifan
|
2d4c200d58
|
[FPGA-Verilog] Now FPGA-Verilog can output shift register bank netlists
|
2021-09-29 20:56:02 -07:00 |
tangxifan
|
f456c7e236
|
[Engine] Add a new API to the MemoryBankShiftRegisterBank to access all the unique modules
|
2021-09-29 20:34:25 -07:00 |
tangxifan
|
b87b7a99c5
|
[Engine] Add MemoryBankShiftRegisterBanks to openfpga context because their contents are required by netlist writers as well as bitstream generators
|
2021-09-29 20:21:46 -07:00 |
tangxifan
|
8f0ae937bc
|
[Engine] Upgraded fabric generator to support single shift register bank per configuration region for QuickLogic memory bank
|
2021-09-29 16:57:49 -07:00 |
tangxifan
|
ac6268d9ae
|
[Engine] Bug fix on compilation errors
|
2021-09-29 16:24:36 -07:00 |
tangxifan
|
c5ae93f177
|
[Engine] Upgraded fabric generator to support shifter register banks in Quicklogic memory bank
|
2021-09-29 16:17:40 -07:00 |
tangxifan
|
5da8f1db73
|
[Engine] Upgrading fabric generator to connect nets between top module and BL/WL shift register modules
|
2021-09-28 23:27:47 -07:00 |
tangxifan
|
7723e00e6c
|
[Engine] Adding the function that builds a shift register module for BL/WLs
|
2021-09-28 22:49:24 -07:00 |
tangxifan
|
834bdd2b07
|
[Engine] Updating fabric generator to support BL/WL shift registers. Still WIP
|
2021-09-28 17:29:03 -07:00 |
tangxifan
|
afd03d7eb7
|
[Engine] Add more check codes for the CCFF circuit model used by BL/WL shift registers
|
2021-09-28 15:56:07 -07:00 |
tangxifan
|
0d72e115ac
|
[Engine] Bug fix for the undriven WLR nets in top-level modules
|
2021-09-28 11:53:38 -07:00 |
tangxifan
|
33e9b27cb8
|
[Engine] Fixed a critical bug when building final bitstream, which may cause loss when merging BLs
|
2021-09-25 20:22:27 -07:00 |
tangxifan
|
29c351f5a4
|
[Engine] Bug fix in estimating the configuration cycles for Verilog testbench generator
|
2021-09-25 19:34:21 -07:00 |
tangxifan
|
e06ac11630
|
[Engine] Bug fix
|
2021-09-25 19:21:16 -07:00 |
tangxifan
|
3cf31f1565
|
[Engine] Fixed bugs
|
2021-09-25 18:22:55 -07:00 |
tangxifan
|
a56d1f4fdb
|
[FPGA-Verilog] Upgraded testbench generator to support memory bank using flatten BL/WLs
|
2021-09-25 17:49:15 -07:00 |
tangxifan
|
386812777c
|
[FPGA-Bitstream] Upgraded bitstream writer to support flatten BL/WLs
|
2021-09-25 12:49:32 -07:00 |
tangxifan
|
1a2a2a6e63
|
[FPGA-Bitstream] Relax fabric bitstream address check
|
2021-09-25 12:03:33 -07:00 |
tangxifan
|
8b72447dad
|
[FPA-Bistream] Updating fabric bitstream writer to organize bitstream for flatten BL/WLs
|
2021-09-24 18:07:07 -07:00 |
tangxifan
|
a49e3fe57a
|
[FPGA-bitstream] Upgraded bitstream generator to support flatten BL/WLs for QL memory bank
|
2021-09-24 16:30:18 -07:00 |
tangxifan
|
2de4a460a8
|
[Engine] Rework the function that counts the number of configurable children for fabric key writer and bitstream generator
|
2021-09-24 15:15:32 -07:00 |
tangxifan
|
74ffc8578f
|
[Engine] Upgraded fabric generator to support flatten BL/WL bus for memory banks
|
2021-09-24 15:05:25 -07:00 |
tangxifan
|
be4c850d2d
|
[Engine] Split the function to add BL/WL configuration bus connections for support flatten BL/WLs
|
2021-09-24 12:03:35 -07:00 |
tangxifan
|
18257b3fa1
|
[Engine] Update BL/WL port addition for the top-level module in fabric generator
|
2021-09-24 11:07:58 -07:00 |
tangxifan
|
7e27c0caf3
|
[Engine] Upgrading top-module fabric generation to support QL memory bank with flatten BL/WLs
|
2021-09-23 16:16:39 -07:00 |
tangxifan
|
8c281a22b0
|
[Engine] Add check codes to validate circuit models for BL/WL protocols
|
2021-09-23 14:39:16 -07:00 |
tangxifan
|
962acda810
|
[Engine] Bug fix in fabric key generation when computing configurable children
|
2021-09-22 11:09:46 -07:00 |
tangxifan
|
ad432e4d95
|
[Engine] Bug fix in finding the start index of BL/WL for each column/row;
|
2021-09-22 10:20:40 -07:00 |
tangxifan
|
b0a471bdc9
|
[Engine] Bug fix in outputting fabric key with coordinates
|
2021-09-21 15:55:11 -07:00 |
tangxifan
|
7688c0570f
|
[Engine] Support coordinate definition in fabric key file format; Now QL memory bank can accept fabric key
|
2021-09-21 15:08:08 -07:00 |
tangxifan
|
c84c0d4a3f
|
[FPGA-Verilog] Upgrade fpga-verilog to support decoders with WLR
|
2021-09-20 17:07:26 -07:00 |
tangxifan
|
36a4da863c
|
[Engine] Support WLR port in OpenFPGA architecture file and fabric generator
|
2021-09-20 16:05:36 -07:00 |
tangxifan
|
2e45a6143b
|
[Engine] Fix a critical bug which causes flatten memory tests failed
|
2021-09-15 15:11:58 -07:00 |
tangxifan
|
f2aa31ddb1
|
[FPGA-Bitstream] Fix the bug which causes bitstream wrong for QL memory bank
|
2021-09-15 13:45:30 -07:00 |
tangxifan
|
061952b7fa
|
[Engine] Bug fix in computing local WLs for GRID/CB/SB
|
2021-09-15 11:51:00 -07:00 |
tangxifan
|
26b1e48723
|
[Engine] Merge BL/WLs in the Grid/CB/SB modules
|
2021-09-15 11:27:55 -07:00 |
tangxifan
|
4af6413c97
|
[Engine] Fixed a critical bug on WL arrangement; Previously we always consider squart of a local tile. Now we apply global optimization where the number of WLs are determined by the max. number of BLs per column
|
2021-09-10 17:03:44 -07:00 |
tangxifan
|
ba1e277dc9
|
[Engine] Fix a few bugs in the BL/WL arrangement and now bitstream generator is working fine
|
2021-09-10 15:05:46 -07:00 |
tangxifan
|
35c7b09888
|
[Engine] Bug fix for mistakes in calculating number of BLs/WLs for QL memory bank
|
2021-09-09 15:23:29 -07:00 |
tangxifan
|
b787c4e100
|
[Engine] Register QL memory bank as a legal protocol
|
2021-09-09 15:06:51 -07:00 |
tangxifan
|
1aac3197eb
|
[FPGA-Verilog] Upgrade testbench generator to support QL memory bank
|
2021-09-05 21:38:00 -07:00 |
tangxifan
|
6f09f5f7ad
|
[FPGA-Bitstream] Upgrade bitstream generator to support QL memory bank
|
2021-09-05 21:25:58 -07:00 |
tangxifan
|
1085e468e2
|
[Engine] Move most utilized functions for memory bank configuration protocol to a separated source file
|
2021-09-05 20:45:56 -07:00 |
tangxifan
|
475ce2c6d9
|
[Engine] Upgrade fabric generator in support QL memory bank connections
|
2021-09-05 17:49:01 -07:00 |
tangxifan
|
ed80d6b3f4
|
[Engine] Place QL memory bank source codes in a separated source file so that integration to OpenFPGA open-source version is easier
|
2021-09-05 13:23:38 -07:00 |
tangxifan
|
cf2e479d18
|
[Engine] Refactor the TopModuleNumConfigBits data structure
|
2021-09-05 12:01:38 -07:00 |
tangxifan
|
f75456e304
|
[Engine] Update BL/WL estimation function for QL memory bank protocol
|
2021-09-05 11:53:33 -07:00 |
tangxifan
|
5759f5f35b
|
[Engine] Start developing QL memory bank: upgrade infrastructures of fabric builder
|
2021-09-03 17:55:23 -07:00 |
tangxifan
|
e9d29e27e5
|
[Tool] Bug fix
|
2021-07-02 15:32:30 -06:00 |
tangxifan
|
6e6c3e9fa4
|
[Tool] Patch the critical bug in the use of signal polarity in pin constraints
|
2021-07-02 15:26:21 -06:00 |
tangxifan
|
9074bffa68
|
[Tool] Support customized default value in pin constraint file
|
2021-07-01 23:43:19 -06:00 |
tangxifan
|
d0e4f8521f
|
[Tool] Bug fix on the reset stimuli
|
2021-07-01 19:58:54 -06:00 |
tangxifan
|
b5df1f9aeb
|
[Tool] Bug fix for redundant endif in netlists
|
2021-06-29 17:02:16 -06:00 |
tangxifan
|
b83eef47b4
|
[Tool] Bug fix for testbench generation without self checking codes
|
2021-06-29 16:27:29 -06:00 |
tangxifan
|
6a260cadbf
|
[Tool] Remove option ``--no_self_checking`` option but use the existing option ``--reference_benchmark_path`` to achieve the same purpose
|
2021-06-29 15:42:23 -06:00 |
tangxifan
|
7ac7de789e
|
[Tool] Add a new option ``--no_self_checking`` so that users can output a simple testbench without self checking codes
|
2021-06-29 15:26:40 -06:00 |
tangxifan
|
77dddaeb39
|
[Tool] Remove the preprocessing flags ``FORMAL_SIMULATION`` and ``FORMAL_VERIFICAITON`` because now ``write_testbench`` command can be called many times to generate different versions
|
2021-06-29 14:26:33 -06:00 |
tangxifan
|
a3208b332b
|
[Tool] Use 'force' in preconfigured testbenches to avoid instrusive code modification on flip-flop HDL
|
2021-06-29 11:50:53 -06:00 |
tangxifan
|
dfe1db996a
|
[Tool] Remove the hardcoded factor when computing simulation timing; There should be no hidden parameters impacting simulation time
|
2021-06-29 09:56:04 -06:00 |
tangxifan
|
87446a14c3
|
[Tool] Bug fix for the option ``--embed_bitstream none``
|
2021-06-27 19:45:06 -06:00 |
tangxifan
|
991062e9bf
|
[Tool] Bug fix
|
2021-06-25 15:22:42 -06:00 |
tangxifan
|
90163fab6c
|
[Tool] Replace option '--support_icarus_simulator' with a new one '--preload_bitstream <string>'
|
2021-06-25 15:06:07 -06:00 |
tangxifan
|
2bb514c51a
|
[Tool] Support time unit in writing simulation information file
|
2021-06-25 10:33:29 -06:00 |
tangxifan
|
bcc16d732c
|
[Tool] Add new option 'testbench_type' so that simulation task can write different information for different testbenches
|
2021-06-25 10:10:16 -06:00 |
tangxifan
|
67dec810eb
|
[Tool] Remove icarus simulator flag; Reduce the file size of preconfigured fabric wrapper by only output the necessary force/deposit HDL codes
|
2021-06-24 17:27:32 -06:00 |
tangxifan
|
549657e1fb
|
[Tool] Remove out-of-date flag: INITIAL_SIMULATION from code base
|
2021-06-24 17:13:36 -06:00 |
tangxifan
|
5364d8104f
|
[Tool] Add signal_init option to preconfigured fabric wrapper writer
|
2021-06-24 17:07:41 -06:00 |
tangxifan
|
21d1519658
|
[Tool] Remove signal initialization flag; Now the HDL codes will not be outputted unless specified in the option
|
2021-06-24 16:56:28 -06:00 |
tangxifan
|
ce3c80f499
|
Merge branch 'master' into dev
|
2021-06-23 09:15:03 -06:00 |
tangxifan
|
cbbf601edc
|
[Tool] Fix a compiler warning due to uninitialized data structure
|
2021-06-18 16:20:13 -06:00 |
tangxifan
|
fed975c52a
|
[Tool] Add postfix removal support in write_io_mapping command
|
2021-06-18 16:13:50 -06:00 |
tangxifan
|
d9d57aad42
|
[Tool] Added default net type options to verilog testbench generator command
|
2021-06-14 11:37:49 -06:00 |
tangxifan
|
7ade48343c
|
[Tool] Deprecate command 'write_verilog_testbench'
|
2021-06-09 17:06:01 -06:00 |
tangxifan
|
2299ce3157
|
[Tool] Preconfigured testbench writer now supports icarus simulator
|
2021-06-09 13:49:25 -06:00 |
tangxifan
|
3bc8e760db
|
[Tool] Add '--fabric_netlist' option to 'write_preconfigured_testbench' command
|
2021-06-09 11:14:45 -06:00 |
tangxifan
|
89fb672631
|
[Tool] Fine-tune the options of 'write_simulation_task_info' to be straightforward to use
|
2021-06-09 10:49:00 -06:00 |
tangxifan
|
97396eda2b
|
[Tool] Add a new command 'write_simulation_task_info'
|
2021-06-08 22:10:02 -06:00 |
tangxifan
|
d2275b971d
|
[Tool] Add a new command 'write_preconfigured_testbench'
|
2021-06-08 21:53:51 -06:00 |
tangxifan
|
85679c0fe2
|
[Tool] Bug fix in the top testbench switch due to fast configuration
|
2021-06-08 21:32:26 -06:00 |
tangxifan
|
8db19c7af9
|
[Tool] Add a new command 'write_preconfigured_fabric_wrapper'
|
2021-06-08 21:28:16 -06:00 |
tangxifan
|
5075c68418
|
[Tool] Remove duplicated codes on fast configuration
|
2021-06-08 20:58:04 -06:00 |
tangxifan
|
4aef9d5c96
|
[Tool] Remove redundant codes
|
2021-06-07 21:54:01 -06:00 |
tangxifan
|
366dcff75d
|
[Tool] Now 'write_full_testbench' supports flatten(vanilla) configuration protocol
|
2021-06-07 21:49:31 -06:00 |
tangxifan
|
9808b61b36
|
[Tool] Bug fix on the unfit vector size of bit index register in Verilog testbench in some cases
|
2021-06-07 20:06:39 -06:00 |
tangxifan
|
ba75c18378
|
[Tool] Now 'write_full_testbench' supports memory bank configuration protocol
|
2021-06-07 17:40:07 -06:00 |
tangxifan
|
1a5902ca74
|
[Tool] Bug fix in finding pruned bitstream for frame-based protocol when fast configuration is enabled
|
2021-06-07 14:32:56 -06:00 |
tangxifan
|
af298de121
|
[Tool] Patch bugs in the full testbench writing using external bitstream file for frame-based configuration protocol
|
2021-06-07 13:53:32 -06:00 |
tangxifan
|
d644b8f22d
|
[Tool] Support external bitstream file when generating full testbench for frame-based decoder
|
2021-06-07 11:55:11 -06:00 |
tangxifan
|
618b04568f
|
[Tool] Remove unnecessary new line in bitstream file
|
2021-06-04 20:07:42 -06:00 |
tangxifan
|
cf7addb1a6
|
[Tool] Add heads to bitstream plain text file
|
2021-06-04 19:48:48 -06:00 |
tangxifan
|
70fb3a85dc
|
[Tool] Patch fast configuration in bitstream writing
|
2021-06-04 17:23:10 -06:00 |
tangxifan
|
d98be9f87b
|
[Tool] Remove icarus requirement on vcd writing in Verilog testbenches; Since vcd writing commands are standard Verilog
|
2021-06-04 16:45:00 -06:00 |
tangxifan
|
6e69c2d70a
|
[Tool] Patch fast configuration in full Verilog testbench generator
|
2021-06-04 16:34:55 -06:00 |
tangxifan
|
061f832429
|
[Tool] Enable fast configuration when writing fabric bitstream
|
2021-06-04 16:23:40 -06:00 |
tangxifan
|
81048d3698
|
[Tool] Add option '--fast_configuration' to 'write_full_testbench' command
|
2021-06-04 11:26:39 -06:00 |
tangxifan
|
98308133c1
|
[Tool] Add configuration skip capability to top testbench which loads external bitstream file
|
2021-06-04 11:24:05 -06:00 |
tangxifan
|
adb18d28b8
|
[Tool] Remove unused arguments
|
2021-06-04 10:37:28 -06:00 |
tangxifan
|
67485269d3
|
Merge branch 'master' into testbench_external_bitstream
|
2021-06-03 15:46:25 -06:00 |
tangxifan
|
ae6a46cd60
|
[Tool] Add a new command write_full_testbench which outputs self-testable full testbench which loads external bitstream file; Currently only support configuration chain without fast configuration technique
|
2021-06-03 15:41:11 -06:00 |
tangxifan
|
1fd399736d
|
[Tool] Patch FPGA-SDC to consider time unit in global port timing constraints
|
2021-05-27 10:26:20 -06:00 |
tangxifan
|
c4ecc9ee7c
|
[Tool] Patch data type of report bitstream distribution command-line option
|
2021-05-07 11:44:01 -06:00 |
tangxifan
|
db9bb9124e
|
[Tool] Add report bitstream distribution command to openfpga shell
|
2021-05-07 11:41:25 -06:00 |
tangxifan
|
8728fd9561
|
[Tool] Typo fix to resolve clang errors
|
2021-04-27 15:06:07 -06:00 |
tangxifan
|
c5d36757c6
|
[Tool] Fix typo in io mapping writing
|
2021-04-27 14:39:57 -06:00 |
tangxifan
|
43c1e052ef
|
[Tool] Add a writer to output I/O mapping information to XML files
|
2021-04-27 14:30:16 -06:00 |
tangxifan
|
148da80869
|
[Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes
|
2021-04-24 14:53:29 -06:00 |
tangxifan
|
0709e5bb81
|
[Tool] Fixed a bug in the routing trace finder for direct connections inside repacker
|
2021-04-24 13:27:44 -06:00 |
tangxifan
|
56948244bc
|
[Tool] Patch a critical bug in pb pin fixup
|
2021-04-22 16:19:54 -06:00 |
tangxifan
|
96ce6b545f
|
[Tool] Patch repack to consider design constraints for pins that are not equivalent
|
2021-04-21 13:53:08 -06:00 |
tangxifan
|
0aec30bac6
|
[Tool] Update FPGA core engine to support mux default path overloading through bitstream setting file
|
2021-04-19 15:53:33 -06:00 |
tangxifan
|
0b49c22682
|
[Tool] Now Verilog testbench generator support adding dedicated stimuli for reset signals from benchmarks
|
2021-04-18 16:11:11 -06:00 |
tangxifan
|
6550ea3dfa
|
[Tool] Rework pin constarint API to avoid expose raw data to judge for developers
|
2021-04-18 12:02:49 -06:00 |
tangxifan
|
6e9b24f9bf
|
[Tool] Patch the invalid pin constraint net name
|
2021-04-17 19:56:30 -06:00 |
tangxifan
|
253422e7b7
|
[Tool] Bugfix due to refactoring
|
2021-04-17 19:27:03 -06:00 |
tangxifan
|
02ca51d84b
|
[Tool] Reorganize functions in full testbench generator to avoid big-chunk codes
|
2021-04-17 17:45:50 -06:00 |
tangxifan
|
d95a1e2776
|
[Tool] Encapulate search function in PinConstraint data structure
|
2021-04-17 17:31:55 -06:00 |
tangxifan
|
da619fabe7
|
[Tool] FPGA-Verilog testbench generator accepts pin constraints in full testbench
|
2021-04-17 17:19:34 -06:00 |
tangxifan
|
6e1b58f8a6
|
[Tool] Update FPGA-Verilog testbench generator to accept pin constraints to non-clock global ports
|
2021-04-17 15:05:22 -06:00 |
tangxifan
|
7c6e000be8
|
[Tool] bug fix
|
2021-04-10 15:36:02 -06:00 |
tangxifan
|
03b68a1fdd
|
[Tool] Reworked fabric bitstream XML writer to consider multiple configuration regions
|
2021-04-10 15:25:39 -06:00 |
tangxifan
|
934918d9c0
|
[Tool] Reworked fabric bitstream output file in plain text format; Support multiple regions
|
2021-04-10 15:06:53 -06:00 |
tangxifan
|
4b8f5f294a
|
[Tool] Capsulate fabric bitstream organization for configuration chain
|
2021-04-10 14:28:31 -06:00 |
tangxifan
|
afa0e751da
|
[Tool] Use alias for complex bitstream data types
|
2021-04-10 14:12:02 -06:00 |
tangxifan
|
902c4cf9e9
|
Merge branch 'master' into dev
|
2021-03-18 15:14:14 -06:00 |
tangxifan
|
3ef292bdbb
|
Merge branch 'netlist_name_patch' of https://github.com/LNIS-Projects/OpenFPGA into netlist_name_patch
|
2021-03-17 20:28:40 -06:00 |
tangxifan
|
fa11410425
|
[Tool] Remove exceptions on outputing verilog port with lsb=0
|
2021-03-17 20:27:08 -06:00 |
tangxifan
|
62a846197b
|
Merge branch 'master' into dev
|
2021-03-15 10:06:34 -06:00 |
tangxifan
|
87006e1374
|
Merge branch 'master' into netlist_name_patch
|
2021-03-15 10:06:24 -06:00 |
tangxifan
|
024aa5cbe4
|
Merge branch 'master' into dev
|
2021-03-15 09:13:18 -06:00 |
tangxifan
|
d2fbda4070
|
Merge branch 'master' into netlist_name_patch
|
2021-03-15 09:13:04 -06:00 |
tangxifan
|
b080bcf018
|
Merge branch 'master' into ganesh_dev
|
2021-03-15 09:12:50 -06:00 |
Maciej Kurc
|
02967f2870
|
Added writing rr graph node indices to GSB dump.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
|
2021-03-15 09:28:38 +01:00 |
tangxifan
|
c8d41b4e69
|
[Tool] Change routing module port naming to include architecture port names
|
2021-03-14 19:35:49 -06:00 |
tangxifan
|
956b9aca01
|
[Tool] Trim dead codes in port naming function
|
2021-03-13 20:23:08 -07:00 |
tangxifan
|
2c5634ee76
|
[Tool] Change pin naming of grid modules to be related to architecture port names
|
2021-03-13 20:05:18 -07:00 |
tangxifan
|
07257d0ff0
|
[Tool] Patch wrong paths in FPGA-SDC
|
2021-03-13 10:58:03 -07:00 |
tangxifan
|
d877a02534
|
[Tool] Patch the extended bitstream setting support on mode-select bits
|
2021-03-10 21:28:09 -07:00 |
tangxifan
|
85640a7403
|
[Tool] Extend bitstream setting to support mode bits overload from eblif file
|
2021-03-10 20:45:48 -07:00 |
tangxifan
|
e34380a654
|
Merge branch 'master' into default_net_type
|
2021-03-01 08:38:58 -07:00 |
tangxifan
|
521e1850c8
|
[Tool] Correct syntax errors for timing definition in verilog for iverilog 10.1
|
2021-02-28 17:04:27 -07:00 |
tangxifan
|
73461971d2
|
[Tool] Bug fix for printing single-bit ports in Verilog netlists
|
2021-02-28 16:12:57 -07:00 |
tangxifan
|
15e26a5602
|
[Tool] Support default_net_type Verilog syntex in fabric generator
|
2021-02-28 11:57:40 -07:00 |
tangxifan
|
df7b436ac7
|
[Tool] Patch repacker to support duplicated nets due to adder nets
|
2021-02-23 19:01:18 -07:00 |
tangxifan
|
e6091fb3ff
|
[Tool] Now throw fatal error on mismatch in configurable regions between fabric key and architecture definition
|
2021-02-18 21:56:30 -07:00 |
tangxifan
|
a5b8b2a64a
|
[Tool] Use dedicated function to identify wire LUT created by repacker
|
2021-02-18 19:37:44 -07:00 |
tangxifan
|
aae03482f5
|
[Tool] Bug fix for wire LUT identification by repacker. Create a dedicated function to identify these LUTs and store the results in shared database
|
2021-02-18 19:37:17 -07:00 |
tangxifan
|
61012897cd
|
[Tool] Bug fix for truth table creation for wired LUT created by repacking algorithm
|
2021-02-17 15:31:20 -07:00 |
tangxifan
|
af4cc117fb
|
[Tool] bug fix in spypad lut
|
2021-02-09 22:53:18 -07:00 |
tangxifan
|
6a0f4f354f
|
[Tool] Support superLUT circuit model in core engine
|
2021-02-09 20:23:05 -07:00 |
tangxifan
|
0c409b5bcc
|
[Tool] Add bitstream annotation support
|
2021-02-01 20:49:36 -07:00 |
tangxifan
|
f102e84497
|
[Tool] Add bitstream setting file to openfpga library
|
2021-02-01 17:43:46 -07:00 |
tangxifan
|
4b77a3a574
|
[Tool] Now activity file is not a manadatory input of openfpga tools
|
2021-01-29 11:33:40 -07:00 |
tangxifan
|
d9fda31a9f
|
[Tool] Add --version to openfpga shell option and a command to openfpga shell
|
2021-01-27 16:03:46 -07:00 |
tangxifan
|
fd0e73a9bb
|
[Tool] Enhance return code for openfpga shell
|
2021-01-24 14:48:27 -07:00 |
tangxifan
|
8cac3291cb
|
[Tool] Add batch mode to openfpga shell execution
|
2021-01-24 14:33:58 -07:00 |
ganeshgore
|
d502410b40
|
Merge pull request #179 from lnis-uofu/unused_gpout_patch
Avoid to output initial signal for general-purpose output ports of FPGA fabrics in Verilog testbenches
|
2021-01-23 18:27:54 -07:00 |
tangxifan
|
4cc8b08a6c
|
[Tool] Add openfpga version display
|
2021-01-23 16:38:00 -07:00 |
tangxifan
|
d2defebee9
|
[Tool] Avoid to output initial signal for general-purpose output ports of FPGA fabrics in Verilog testbenches
|
2021-01-22 16:42:13 -07:00 |
tangxifan
|
3f80a26172
|
[Tool] Bug fix for combinational benchmarks in pre-config testbench generation
|
2021-01-19 18:22:50 -07:00 |
tangxifan
|
75b99b78e9
|
[Tool] Now testbench generator consider pin constraints in generating clock sources for benchmarks
|
2021-01-19 17:38:51 -07:00 |
tangxifan
|
da200658c1
|
[Tool] Now autocheck top testbench consider pin constraints to generate operating clock sources for benchmarks
|
2021-01-19 17:29:59 -07:00 |
tangxifan
|
0670c2de59
|
[Tool] Deploy pin constraints to preconfig Verilog module generation
|
2021-01-19 16:56:30 -07:00 |
tangxifan
|
8c311b8282
|
[Tool] Bug fix in repacker for considering design constraints
|
2021-01-17 12:26:14 -07:00 |
tangxifan
|
2efe513122
|
[Tool] Now repack consider design constraints; test pending
|
2021-01-16 21:57:17 -07:00 |
tangxifan
|
bb8e7e25c2
|
[Tool] Start deploying design constraints in repack engine
|
2021-01-16 21:27:12 -07:00 |
tangxifan
|
fa67517349
|
[Tool] Add repack design constraints to openfpga command 'repack'
|
2021-01-16 18:49:34 -07:00 |
tangxifan
|
ad7a54db1b
|
[Tool] Add repack dc library to compilation
|
2021-01-16 17:20:59 -07:00 |
tangxifan
|
87b2c1f3b8
|
[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation
|
2021-01-15 12:01:53 -07:00 |
tangxifan
|
852f5bb72e
|
[Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers
|
2021-01-14 15:38:24 -07:00 |
tangxifan
|
9cc9e45b4b
|
[Tool] Apply a dirty fix to Verilog testbench generator so that multi-clock testbench can be generated
|
2021-01-13 15:13:19 -07:00 |
tangxifan
|
c0da6b900a
|
[Tool] Bug fix in creating multi-bit clock port connections
|
2021-01-12 18:38:00 -07:00 |
tangxifan
|
65b2fe3ab7
|
[Tool] Bug fix in the global tile connection by considering all the subtiles
|
2021-01-10 11:52:38 -07:00 |
tangxifan
|
9a441fa5cc
|
[Tool] Upgrade openfpga to support extended global tile port definition
|
2021-01-09 18:47:12 -07:00 |
tangxifan
|
cde26597ed
|
[Tool] Bug fix in scan chain builder calling
|
2021-01-04 18:45:47 -07:00 |
tangxifan
|
804b721a19
|
[Tool] Bug fix in the configuration chain connection builder
|
2021-01-04 17:41:29 -07:00 |
tangxifan
|
bfd305b5a5
|
[Tool] Patch the bug in finding data output ports for CCFF
|
2021-01-04 17:22:30 -07:00 |
tangxifan
|
cc91a0aebd
|
[Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder
|
2021-01-04 17:14:26 -07:00 |
tangxifan
|
d11a3d9fef
|
[Tool] Avoid outputting signal initialization codes because they are bulky
|
2020-12-06 14:29:16 -07:00 |
tangxifan
|
cb2bd2e31c
|
[Tool] Remove register ports for mini local encoders (1-bit data out)
|
2020-12-06 14:21:54 -07:00 |
tangxifan
|
6bdfcb0147
|
[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming
|
2020-12-05 12:44:09 -07:00 |
tangxifan
|
6f18688f0e
|
[Tool] Now routing multiplexer in the same circuit model (regardless or input sizes) can share the same primitive module
|
2020-12-05 10:53:01 -07:00 |
tangxifan
|
0da92ad888
|
[Tool] Split MUX Verilog netlist into two separated files: one contains only primitives while the other contains the top-level modules
|
2020-12-04 22:16:51 -07:00 |
tangxifan
|
5be9e9b736
|
[Tool] Adapted tools to support I/O in center grid
|
2020-12-04 18:50:13 -07:00 |
tangxifan
|
73aaa261d8
|
[Tool] Relax the IO restriction in pb_pin post-routing packing fix-up
|
2020-12-04 17:55:25 -07:00 |
tangxifan
|
4aa6264b1c
|
[Tool] Rework simulation time period to be sync with actual stimuli
|
2020-12-02 22:58:13 -07:00 |
tangxifan
|
b661c39b04
|
[Tool] Force the number of simulation clock cycles to be >= 2 to avoid false-positive self-testing in testbenches
|
2020-12-02 19:36:36 -07:00 |