Commit Graph

1311 Commits

Author SHA1 Message Date
tangxifan b780f0a552 [core] code format 2023-11-03 14:39:49 -07:00
tangxifan e48de682ed [core] fixed som ebugs 2023-11-03 14:39:28 -07:00
tangxifan b2e1eb30c7 [core] code format 2023-11-03 13:50:04 -07:00
tangxifan 21813eb59f [core] now full testbench uses bitstream in different sizes 2023-11-03 13:48:21 -07:00
tangxifan 2cd3453629 [core] fixed the bug in ccff v2 on config enable signal drivers 2023-11-03 10:25:12 -07:00
tangxifan 8bee65853c [core] add missing files 2023-11-02 19:01:25 -07:00
tangxifan 649d44b2d8 [core] code format 2023-11-02 16:33:55 -07:00
tangxifan 36fa020c15 [core] syntax 2023-11-02 16:33:19 -07:00
tangxifan 75e9e98e5d [core] add two new commands to output testbench parts 2023-11-02 16:06:48 -07:00
tangxifan 3d4f1505b6 [core] code format 2023-10-20 22:02:56 -07:00
tangxifan 66c3226fad [core] now follow module unique index when naming grouped configuration memories 2023-10-20 22:01:19 -07:00
tangxifan e4b204f2e4 [core] code format 2023-10-20 21:14:07 -07:00
tangxifan 76a4b8a82b [core] remove the prefix of grouped memory blocks 2023-10-20 21:13:37 -07:00
tangxifan 5bae2bf54d [core] code format 2023-10-19 23:05:49 -07:00
tangxifan 4b00651a46 [core] now name indexing is applied to netlist names 2023-10-19 23:03:48 -07:00
tangxifan 7ba6795fe2 [core] fixed a bug 2023-10-06 18:50:26 -07:00
tangxifan 83ef35b2da [core] fixed a bug 2023-10-06 18:47:20 -07:00
tangxifan 3440768840 [core] code format 2023-10-06 18:37:54 -07:00
tangxifan e102c9bddc [core] fixed a bug 2023-10-06 18:37:28 -07:00
tangxifan 93cbbf2045 [core] code format 2023-10-06 18:20:55 -07:00
tangxifan b07111497c [core] enable options in xml writers 2023-10-06 18:20:17 -07:00
tangxifan ae63c9d441 [core] code format 2023-10-06 17:28:25 -07:00
tangxifan 1e8bf1cece [core] deploy options 2023-10-06 17:28:02 -07:00
tangxifan f30663f708 [core] code format 2023-10-06 14:08:09 -07:00
tangxifan 108bbad8d4 [core] syntax 2023-10-06 14:07:44 -07:00
tangxifan 80856f1b70 [core] adding new options and rewrite options for bitfile writer 2023-10-06 13:54:29 -07:00
tangxifan a15db83267 [core] code format 2023-09-26 11:41:11 -07:00
tangxifan ea91182216 [core] check option conflicts 2023-09-26 11:40:42 -07:00
tangxifan c4bce834e4 [core] code format 2023-09-25 22:34:39 -07:00
tangxifan 5aa206e616 [core] fixed some bugs 2023-09-25 22:27:24 -07:00
tangxifan 1624dc9764 [core] code format 2023-09-25 21:13:50 -07:00
tangxifan 76f446caec [core] fixed a bug 2023-09-25 21:13:11 -07:00
tangxifan dbd466cdec [core] now support tile port merge 2023-09-25 18:16:24 -07:00
tangxifan 3adf81046a [core] code format 2023-09-25 17:22:26 -07:00
tangxifan 5e269e8bc4 [core] support port merging at grid modules 2023-09-25 17:21:58 -07:00
tangxifan edb0e687f1 [core] code format 2023-09-23 12:15:53 -07:00
tangxifan 11de8965a8 [core] fixed some bugs 2023-09-23 12:15:31 -07:00
tangxifan 860cfd53c6 [core] fixed critical bugs in renaming modules 2023-09-23 11:51:31 -07:00
tangxifan ca3617a029 [core] code format 2023-09-20 20:37:27 -07:00
tangxifan 1ef38b6a64 [core] now name the port of tiles using the relative index of the subblocks in each tile, rather than the unique index of subblocks across a complete fabric. This avoids all the conflicts in naming 2023-09-20 20:34:21 -07:00
tangxifan c105b56bf0 [core] code format 2023-09-18 23:31:27 -07:00
tangxifan 43fd08a3fe [core] fixed a bug 2023-09-18 23:31:09 -07:00
tangxifan 4d11f73471 [core] fixed a bug 2023-09-18 20:43:15 -07:00
tangxifan a1e609c901 [core] fixed some bugs 2023-09-18 16:39:07 -07:00
tangxifan 1daabb990e [core] code format 2023-09-18 15:35:13 -07:00
tangxifan 110301a2e4 [core] now tile port naming can follow index 2023-09-18 15:34:40 -07:00
tangxifan e46e58527a [core] code format 2023-09-17 23:16:38 -07:00
tangxifan eeb1bd6662 [core] fixed some bugs 2023-09-17 23:16:15 -07:00
tangxifan c6175aa514 [core] code format 2023-09-17 22:37:48 -07:00
tangxifan ef97127c63 [core] fixed some bugs in testbenches when renaming top modules 2023-09-17 22:34:00 -07:00