Commit Graph

3704 Commits

Author SHA1 Message Date
tangxifan 86387ff79c Merge branch 'refactoring' into dev 2019-10-05 18:15:31 -06:00
tangxifan c920047ee8 refactored Verilog generation for connection blocks 2019-10-05 18:14:23 -06:00
AurelienUoU 0983f85684 Merge remote-tracking branch 'origin/dev' into heterogeneous 2019-10-05 12:46:34 -06:00
Baudouin Chauviere 027272c976 Faster regression test 2019-10-05 12:10:55 -06:00
tangxifan 2d7e8d9811 add check codes for memory buses 2019-10-05 11:07:26 -06:00
tangxifan 6b301d9f44 Merge branch 'dev' into refactoring 2019-10-04 22:47:29 -06:00
tangxifan b905c0c68c refactored memory module Verilog generation for scan-chains 2019-10-04 22:45:45 -06:00
AurelienUoU 7aa24f407e Fix explicit port name in CBs 2019-10-04 11:20:46 -06:00
Baudouin Chauviere 6f7023658e Revert "Correction on the cb vs sb corrdinator. Does not fix the problem though"
This reverts commit 95596bb4f8.
2019-10-03 14:59:04 -06:00
Baudouin Chauviere 95596bb4f8 Correction on the cb vs sb corrdinator. Does not fix the problem though 2019-10-03 13:50:01 -06:00
Baudouin Chauviere db059af8b8 Lighten the regression test 2019-10-03 13:33:28 -06:00
Baudouin Chauviere c7e1f7d90b Added explicit_verilog to regression test in a clean way 2019-10-03 10:17:04 -06:00
Baudouin Chauviere 01ff484158 Explicit verilog passing all tests 2019-10-02 10:22:28 -06:00
Baudouin Chauviere 6b3e1fd410 Get backup verilog_routing.c 2019-10-02 08:54:56 -06:00
Baudouin Chauviere 829cbcfbe3 Merge
Merge remote-tracking branch 'origin' into explicit_verilog
2019-10-01 16:54:27 -06:00
Baudouin Chauviere 33e50bbc8c fix 2019-10-01 16:54:16 -06:00
Baudouin Chauviere 7c3ab38410 Hot fix 2019-10-01 16:40:16 -06:00
Baudouin Chauviere 633a12ee08 Buggy version but need help on debugging 2019-10-01 14:49:42 -06:00
AurelienUoU 36f7624b95 Point to point truth table typo fix 2019-10-01 13:07:27 -06:00
AurelienUoU e2867019e1 Typo fixing 2019-09-30 10:38:02 -06:00
AurelienUoU 74f7a3cfb2 Doc fixing 2019-09-30 10:29:42 -06:00
AurelienUoU fdc3c5e4a9 Merge remote-tracking branch 'origin/dev' into heterogeneous 2019-09-30 10:02:11 -06:00
AurelienUoU 5ac79f4805 Point to point documentation 2019-09-30 10:00:46 -06:00
tangxifan b082e60c10 start refactoring instanciation of memory modules 2019-09-29 18:20:56 -06:00
tangxifan 3726e691f4 simplify the local wire generation for ccffs 2019-09-28 21:36:56 -06:00
tangxifan 1983e56557 make local configuration bus generation more general 2019-09-28 21:02:14 -06:00
Ganesh Gore 069f628bb0 Merge branch 'dev' of github.com:LNIS-Projects/OpenFPGA into ganesh_dev 2019-09-28 11:21:37 -06:00
tangxifan 433fc73460 refactored local encoder support for Verilog MUX generation 2019-09-27 23:10:43 -06:00
tangxifan 4da5035627 Connect CCFFs in a chain in a Verilog module 2019-09-27 20:50:12 -06:00
tangxifan f0949fea2f Merge branch 'dev' into refactoring 2019-09-27 18:09:58 -06:00
tangxifan 1e187f3d15 start adding memory circuit to Switch blocks 2019-09-27 18:08:37 -06:00
AurelienUoU 640922accd Merge remote-tracking branch 'origin/dev' into heterogeneous 2019-09-27 16:54:13 -06:00
AurelienUoU a93d7e57f7 Scan chain support in directlist 2019-09-27 16:53:00 -06:00
tangxifan 167778cf57 refactoring MUX Verilog instanciation in Switch block 2019-09-27 16:05:47 -06:00
Ganesh Gore d269472daf Updated formality python script 2019-09-27 14:00:57 -06:00
Ganesh Gore 438b592a8a Appended VPR to genereate INI File 2019-09-27 14:00:27 -06:00
Ganesh Gore a3e9b4aea9 Added mINI/lib - INI Read write to project 2019-09-27 13:58:48 -06:00
tangxifan dbe1625267 Refactored Verilog wiring for formal verification ports in Switch Blocks 2019-09-27 13:51:22 -06:00
tangxifan ead014e7d8 refactoring the configuration bus Verilog generation for MUXes 2019-09-27 11:47:34 -06:00
tangxifan 091bbd4d9c start refactoring the num_config_bits for circuit model 2019-09-26 22:53:07 -06:00
tangxifan 8ccf681749 Merge branch 'dev' into refactoring 2019-09-26 21:00:19 -06:00
tangxifan f0589cc2cf refactoring mux Verilog generation for switch blocks 2019-09-26 20:59:19 -06:00
tangxifan 05eaa412b1 refactored short-connection of switch block 2019-09-26 14:31:05 -06:00
AurelienUoU 3b13c959f3 Finish renaming SCFF to CCFF 2019-09-26 14:04:40 -06:00
AurelienUoU c4449b667f Merge remote-tracking branch 'origin/dev' into heterogeneous 2019-09-26 11:34:59 -06:00
AurelienUoU 056219f180 Rename SCFF to CCFF, configuration chain flip flop 2019-09-26 11:32:57 -06:00
tangxifan ea0da49e04 Merge branch 'dev' into refactoring 2019-09-25 21:06:06 -06:00
tangxifan 5bb40e7f74 refactored local wire generation for Switch block 2019-09-25 21:05:02 -06:00
AurelienUoU e5faeb1400 Merge remote-tracking branch 'origin/dev' into heterogeneous 2019-09-25 16:50:53 -06:00
AurelienUoU a35e2936b2 Fix verilog generation for direct connexion from directlist 2019-09-25 16:44:00 -06:00