Commit Graph

598 Commits

Author SHA1 Message Date
tangxifan b80e26e711 update bitstream generator to use sorted edges 2020-03-08 15:36:47 -06:00
tangxifan 5558932762 use sorted edges in building routing modules 2020-03-08 15:31:41 -06:00
tangxifan f9499afe04 remove unused variable 2020-03-08 15:00:01 -06:00
tangxifan 0c7aa2581d update vpr8 version with hotfix on undriven pins in GSB 2020-03-08 14:58:56 -06:00
tangxifan ca92c2717f bug fix for tile directs 2020-03-07 16:00:32 -07:00
tangxifan 37423729ec bug fixing for naming the duplicated pins 2020-03-07 15:44:57 -07:00
tangxifan 5be118d695 tileable rr_graph builder ready to debug 2020-03-06 16:18:45 -07:00
tangxifan 6e83154703 move rr_gsb and rr_chan to tileable rr_graph builder 2020-03-04 14:14:28 -07:00
tangxifan 4b7d2221d1 adapt rr_graph builder utilized functions and move rr_graph utils from openfpga to vpr 2020-03-04 13:55:53 -07:00
tangxifan 7fcd27e000 now we give explicit instance name to each interconnect inside grid. Thus resolve the problem in sdc writer 2020-03-03 12:29:58 -07:00
tangxifan 3241d8bd37 put analysis sdc writer online. Minor bug in redudant '/' to be fixed 2020-03-02 19:54:18 -07:00
tangxifan 037c7e5c43 adapt top-level function for analysis SDC writer 2020-03-02 17:58:44 -07:00
tangxifan 24f7416c71 adapt analysis SDC writer for grids 2020-03-02 17:15:01 -07:00
tangxifan 6474183539 adapt analysis SDC writer for routing modules 2020-03-02 14:29:58 -07:00
tangxifan 543cff58b9 start porting analysis SDC writer 2020-03-02 13:44:08 -07:00
tangxifan a17c14c363 clean-up command addition and add fabric bitstream building to sample script 2020-03-02 10:39:19 -07:00
tangxifan aa66042dfb move simulation setting annotation to a separated source file 2020-02-29 15:19:02 -07:00
tangxifan 7b18f7cd09 now the auto select number of clocks in simulation is online 2020-02-29 13:29:16 -07:00
tangxifan 3807a940f4 fixed critical bugs in bitstream generation and now we pass microbenchmarks 2020-02-28 16:45:50 -07:00
tangxifan 9fd184e3ab rm out-of-date script 2020-02-28 15:42:18 -07:00
tangxifan 05ebd77d7d start debugging with micro benchmarks. Spot problem in local routing 2020-02-28 15:41:32 -07:00
tangxifan a6c2d2c7d1 bug fixed for io location mapping 2020-02-28 14:46:01 -07:00
tangxifan 80bb2baae5 start verification and bug fixing 2020-02-28 14:29:01 -07:00
tangxifan 542fadaaae allow users to use VPR critical path delay in OpenFPGA simulation 2020-02-28 12:10:27 -07:00
tangxifan de8425874c use user defined critical path delay in SDC generation 2020-02-28 11:24:39 -07:00
tangxifan 092e10afda bring pnr sdc generator online and fixed minor bugs in bitstream writing 2020-02-28 11:14:50 -07:00
tangxifan e45fa18c4c adapt PnR SDC writer 2020-02-28 10:06:35 -07:00
tangxifan 89c51b70e3 split sdc option into two categories which will be called by different commands 2020-02-28 09:48:58 -07:00
tangxifan fdcb982903 adapt pnr sdc grid writer 2020-02-27 21:06:33 -07:00
tangxifan b4ed931ac6 adapt sdc routing writer 2020-02-27 20:35:56 -07:00
tangxifan d136ac236f adapt sdc memory utils 2020-02-27 19:39:57 -07:00
tangxifan 78476ca774 adapt sdc writer utils 2020-02-27 19:36:28 -07:00
tangxifan 8322b1623d start porting SDC generator 2020-02-27 19:30:36 -07:00
tangxifan 65c81e14b2 add simulation ini file writer 2020-02-27 18:01:47 -07:00
tangxifan ae899f3b11 bug fixed for clock names 2020-02-27 16:51:55 -07:00
tangxifan 9b769cd8e4 bug fix for using renamed i/o names 2020-02-27 16:37:20 -07:00
tangxifan b010fc1983 add warning to force formal_verification_top_netlist enabled 2020-02-27 13:28:21 -07:00
tangxifan 078f72320f debugging Verilog testbench generator. Bug spotted in using renamed atom_block and clock ports 2020-02-27 13:24:26 -07:00
tangxifan f558405887 ported verilog testbench generator online. Split from fabric generator. Testing to be done 2020-02-27 12:33:09 -07:00
tangxifan 77529f4957 adapt top Verilog testbench generation 2020-02-26 21:30:21 -07:00
tangxifan bb671acac3 add formal random Verilog testbench generation 2020-02-26 20:58:16 -07:00
tangxifan e9adb4fdbc add preconfig top module Verilog generation 2020-02-26 20:38:01 -07:00
tangxifan b3796b0818 build io location map 2020-02-26 19:58:18 -07:00
tangxifan 25e0583636 add io location map data structure and start porting verilog testbench generator 2020-02-26 17:10:57 -07:00
tangxifan 410dcf6ab6 debugged LUT bitstream 2020-02-26 11:42:18 -07:00
tangxifan a26d31b87f make write bitstream online 2020-02-26 11:09:23 -07:00
tangxifan 759758421d found the bug in physical pb mode bits and fixed 2020-02-25 23:45:49 -07:00
tangxifan 075264e3e3 debugging LUT bitstream generation 2020-02-25 23:29:16 -07:00
tangxifan 4024ed63cb add truth table build up for physical LUTs 2020-02-25 22:39:42 -07:00
tangxifan 2dd80e4830 add more methods to acquire physical truth table from physical pb 2020-02-25 21:21:44 -07:00
tangxifan ca038857d3 add lut physical truth table to physical pb 2020-02-25 13:34:13 -07:00
tangxifan 2d86a02358 refactored LUT bitstream generation to use vtr logic 2020-02-25 12:45:13 -07:00
tangxifan 2c44c70557 bring pb interconnection bitstream generation online 2020-02-25 00:28:06 -07:00
tangxifan 04c69d30c2 start adding grid bitstream builder. TODO: lut and interconnect bitstream decoding 2020-02-24 19:38:02 -07:00
tangxifan 8e9660b816 add mapped block fast look-up as placement annotation 2020-02-24 16:09:29 -07:00
tangxifan 712eeb1340 bring bitstream generator for routing modules online 2020-02-23 22:09:46 -07:00
tangxifan 86c7c24701 add fabric bitstream generation online 2020-02-23 20:58:17 -07:00
tangxifan 8723007f68 Bring mux bitstream generation online 2020-02-23 20:53:24 -07:00
tangxifan 51439ba3b4 add bitstream writer to be integrated 2020-02-23 20:40:18 -07:00
tangxifan 2d17395e13 start integrating fpga_bitstream. Bring data structures online 2020-02-22 23:04:42 -07:00
tangxifan 9583731531 add results saver for lb router 2020-02-22 22:10:32 -07:00
tangxifan 921bf7dd7b use constant in device annotation 2020-02-21 20:45:22 -07:00
tangxifan 926e429374 add save repacking results in physical pb 2020-02-21 20:39:49 -07:00
tangxifan 12f2888c7c add physical pb data structure and basic allocator 2020-02-21 17:47:27 -07:00
tangxifan b035b4c87f debugged with Lbrouter. Next step is to output routing traces to physical pb data structure 2020-02-21 12:16:50 -07:00
tangxifan 1b66e837ba bug fixing for lb router. Add physical mode to default node expanding settings 2020-02-21 11:29:00 -07:00
tangxifan 0b0e00b5f4 debugging the LbRouter 2020-02-20 21:56:15 -07:00
tangxifan 4abaef14b5 bug fixed in pb_pin fix-up. This is due to A CRITICAL BUG IN PHYSICAL_TILE PIN MAPPING!!! 2020-02-20 20:50:59 -07:00
tangxifan 3e07d7d5e0 finish net addition to LbRouter. Found a bug in pb pin fix-up. Need to consider clustered I/O block z offset 2020-02-20 20:26:20 -07:00
tangxifan fdb27c5a6b move lb_rr_graph construction to repack command 2020-02-20 13:24:34 -07:00
tangxifan d8ab5536e1 add advanced check codes for lb_rr_graph 2020-02-19 21:41:05 -07:00
tangxifan ed5d83178f add fundamental check codes for LbRRGraph 2020-02-19 21:07:31 -07:00
tangxifan bc27f9dd0c add check codes for nets inside LbRouter 2020-02-19 20:34:30 -07:00
tangxifan 43f15e4d6f add methods to LbRouter for nets to be routed and access to routing traceback 2020-02-19 16:40:53 -07:00
tangxifan 444b994285 flatten the t_net inside LbRouter into internal data 2020-02-19 15:37:22 -07:00
tangxifan 2b37fcb296 use strong id for nets to be routed in LbRouter 2020-02-19 15:09:25 -07:00
tangxifan 2f1bcdd27d use local data to store illegal modes for pb_graph_node inside LbRouter 2020-02-19 14:53:35 -07:00
tangxifan 5ccb4adb08 refactored LB router main function 2020-02-19 11:09:24 -07:00
tangxifan 3d5a15d41e refactored most functions except echo and try_route() in LbRouter 2020-02-19 00:07:36 -07:00
tangxifan 80fa6f8a0a refactored skip nets in LbRouter 2020-02-18 22:08:51 -07:00
tangxifan 289c869caf refactored expand rt_node in LbRouter 2020-02-18 22:01:22 -07:00
tangxifan c7ef14fc23 refactoring node expansion in LbRouter 2020-02-18 21:51:03 -07:00
tangxifan 11879d43b4 add methods one by one to LbRouter from cluster_router.cpp 2020-02-18 19:22:36 -07:00
tangxifan 0310dafe42 add accessors to LBRouter 2020-02-18 18:35:00 -07:00
tangxifan 1799db810d compilation error fix 2020-02-18 17:04:36 -07:00
tangxifan d58d14df8e start encapsulate the whole lb router in an object 2020-02-18 16:50:56 -07:00
tangxifan ed25ccc70f start refactoring lb router in openfpga namespace 2020-02-18 12:00:27 -07:00
tangxifan 6060440b97 fine tuning for the verbose output 2020-02-17 21:14:15 -07:00
tangxifan 409b3f6896 add lb_rr_graph builder for the refactored version 2020-02-17 21:11:56 -07:00
tangxifan 8e97443410 start working on repack 2020-02-17 17:57:43 -07:00
tangxifan 62e4f14e30 add lb_rr_graph to device annotation 2020-02-17 17:26:27 -07:00
tangxifan 6c69b52ded Add missing file 2020-02-17 17:11:29 -07:00
tangxifan 92076c1460 refactored lb_rr_graph in the same principle of RRGraph object 2020-02-17 16:59:24 -07:00
tangxifan 60f40a9657 use constant module manager as much as possible in Verilog writer 2020-02-16 16:35:26 -07:00
tangxifan 11775c370b bring FPGA top module verilog writer online. Fabric Verilog generator done 2020-02-16 16:18:14 -07:00
tangxifan e37ac8a098 add grid module Verilog writer 2020-02-16 16:04:41 -07:00
tangxifan c20caa1fa3 routing module Verilog writer is online 2020-02-16 14:47:54 -07:00
tangxifan c6c3ef71f3 adapt all the Verilog submodule writers and bring it onlien 2020-02-16 13:35:18 -07:00
tangxifan 99c3712b6f adapt Verilog wire module writer 2020-02-16 12:59:37 -07:00
tangxifan 5cc68b0730 adapt LUT Verilog writer 2020-02-16 12:45:58 -07:00
tangxifan 105ccabecc adapt memroy writer for verilog 2020-02-16 12:41:43 -07:00
tangxifan c9d8120ae0 adapt Verilog mux writer 2020-02-16 12:35:41 -07:00
tangxifan a88c4bc954 add decode utils to libopenfpga and adapt local decoder writer in Verilog 2020-02-16 12:21:59 -07:00
tangxifan 3efd1a2a6d print verilog module writer online 2020-02-16 12:04:03 -07:00
tangxifan cf34339e96 adapt essential gates for submodule generation 2020-02-16 11:57:19 -07:00
tangxifan 2eba882332 put verilog submodules online. ready to bring the how submodule writer online 2020-02-16 11:41:20 -07:00
tangxifan 4cb61e2138 bring preprocessing flag Verilog netlists online 2020-02-16 00:03:24 -07:00
tangxifan 0d5292ad0d adapt verilog writer utils 2020-02-15 23:26:59 -07:00
tangxifan bf54be3d00 add option data structure for FPGA Verilog 2020-02-15 21:39:47 -07:00
tangxifan da79ef687c add missing files 2020-02-15 20:54:37 -07:00
tangxifan 8b0df8632c bring fpga verilog create directory online 2020-02-15 20:38:45 -07:00
tangxifan 622c7826d1 start transplanting fpga_verilog 2020-02-15 15:03:00 -07:00
tangxifan 85627dc128 put build top module online 2020-02-15 14:13:32 -07:00
tangxifan 539f13720a tile direct supports inter-column/inter-row direct connections 2020-02-15 13:42:53 -07:00
tangxifan 213c611c0b add tile direct builder 2020-02-14 22:21:32 -07:00
tangxifan 7e86cf1079 add tile direct data structure 2020-02-14 19:11:49 -07:00
tangxifan 59c13550e0 add direct annotation with inter-column/row syntax 2020-02-14 17:40:59 -07:00
tangxifan c855ab24f5 put build top module memory connections online 2020-02-14 11:07:04 -07:00
tangxifan 9dc9c2c9f7 add build top module connection functions 2020-02-14 10:45:24 -07:00
tangxifan 36179b6ced start moving top-module builder. Now adapt the utils 2020-02-14 10:00:24 -07:00
tangxifan afe8278670 put routing module builder online 2020-02-13 17:35:29 -07:00
tangxifan cf440f92d3 put routing module builder util function online 2020-02-13 16:05:23 -07:00
tangxifan 89086ed080 add verbose output to build grid module 2020-02-13 15:38:26 -07:00
tangxifan 072965cd64 make grid module builder online; basic support on physical tiles 2020-02-13 15:27:16 -07:00
tangxifan 59d579425e add utils for duplicate pins in grid module builder 2020-02-12 20:48:07 -07:00
tangxifan 895d5b5a0a add utils for grid module builder 2020-02-12 20:25:05 -07:00
tangxifan 002c2795fe add memory module builder 2020-02-12 20:06:38 -07:00
tangxifan 8e381f0581 add wire module builder 2020-02-12 19:57:15 -07:00
tangxifan e842150cc5 add lut module builder 2020-02-12 19:52:41 -07:00
tangxifan fddd3c9463 add mux module builder 2020-02-12 19:45:14 -07:00
tangxifan ea7d879b4f add decoder module builder 2020-02-12 18:28:50 -07:00
tangxifan f11832b8cf start integrating module graph builder 2020-02-12 17:53:23 -07:00
tangxifan 13fadd0f91 move compact routing hierarchy to build_fabric command 2020-02-12 15:49:47 -07:00
tangxifan c78d3e9af1 add mux library builder 2020-02-12 14:58:23 -07:00
tangxifan ce63b1cc62 add circuit model binding for direct connections and enhance model type checking 2020-02-12 11:40:20 -07:00
tangxifan 4a05cec037 add rr_segment binding to circuit model 2020-02-12 11:21:40 -07:00
tangxifan a736e09c29 add rr_switch binding in link openfpga arch command 2020-02-12 10:52:20 -07:00
tangxifan feccbc5780 add more methods to link routing to circuit models in device annotation 2020-02-12 10:08:54 -07:00
tangxifan a31d6c6d1e rename pb_type annotation to device annotation 2020-02-12 09:52:18 -07:00
tangxifan 4367dba9b7 move mux graph and decoder builders to vpr8 integration; ready to link the rr_switch to circuit models 2020-02-11 21:02:58 -07:00
tangxifan 175bef014a add compact_routing hierarchy command 2020-02-11 17:40:37 -07:00
tangxifan 1372f748f1 put GSB builder online 2020-02-11 16:37:14 -07:00
tangxifan 85f3826939 put device rr_gsb online. Ready to plug-in 2020-02-09 14:58:23 -07:00
tangxifan 230c7b709a put rr_gsb data structure online 2020-02-09 00:20:44 -07:00
tangxifan 0b6b3bc029 start adapting rr_gsb related data structure 2020-02-07 11:32:33 -07:00
tangxifan 3d7eff64b9 bug fixed for lut truth table fixup. Results look good 2020-02-06 17:47:25 -07:00
tangxifan ed9e038845 add functionality of LUT truth table fix-up 2020-02-06 17:14:29 -07:00
tangxifan 99f5a86b49 bug fixed for routing annotation and routing net fix-up 2020-02-06 12:54:55 -07:00
tangxifan cccbb9fd49 add missing files 2020-02-05 22:12:44 -07:00
tangxifan dad204674b done an initial version of clustering net fix-up based on routing results. Debugging on the way 2020-02-05 21:50:52 -07:00
tangxifan 5006a4395d bring RRGraph object and writer online 2020-01-31 16:39:40 -07:00
tangxifan 75c3507acf add verbose output option for openfpga linking architecture 2020-01-31 11:36:58 -07:00
tangxifan 392ab0f027 move duplicated codes on message printing to functions 2020-01-31 10:53:41 -07:00
tangxifan afde9808da add check codes for physical pb_graph_node and pb_graph_pin annotation 2020-01-31 10:47:05 -07:00
tangxifan fdc304a0fb fixed a bug in mapping pb_graph pins using rotation offset 2020-01-30 22:00:53 -07:00
tangxifan 02d6256e95 pass simple test on pb_type annotation for frac_lut5 architecture 2020-01-30 21:39:44 -07:00
tangxifan 007e1997e6 add pb_graph pin annotation 2020-01-30 19:40:40 -07:00
tangxifan d62c9fe86f adding pb_graph_node annotation 2020-01-30 16:40:13 -07:00
tangxifan e48ab8cb44 move annotation source files to a separated folder 2020-01-30 13:37:41 -07:00
tangxifan 568ed120c2 change report naming fix-up to be XML format 2020-01-29 21:53:56 -07:00
tangxifan f28ca3ffd0 add more echo to log 2020-01-29 18:58:57 -07:00
tangxifan 87f1ca1151 add naming fix-up report generation 2020-01-29 18:56:47 -07:00
tangxifan 2dc4c26257 add naming fix-up 2020-01-29 17:49:33 -07:00
tangxifan 8c86c0af04 add check netlist naming conflict command and functions 2020-01-29 16:23:41 -07:00
tangxifan d2c47693f6 add check codes for mode bits annotation to pb_types and clean up utils source files 2020-01-29 14:29:00 -07:00
tangxifan a4381563bc move check codes to separated source files 2020-01-29 13:47:59 -07:00
tangxifan b67358d2c5 add check codes for physical pb_type circuit model annotation 2020-01-29 12:56:49 -07:00
tangxifan a722438fa3 add mode bits binding to pb_type annotation 2020-01-29 12:27:55 -07:00
tangxifan 61b487eb75 show more information in the log file 2020-01-29 11:29:41 -07:00
tangxifan 399ba8d648 add pb type port mapping to circuit model ports 2020-01-29 11:24:14 -07:00
tangxifan cf3c5b5c42 add circuit model type checking for physical pb_type annotation 2020-01-29 10:41:02 -07:00
tangxifan 8a7a4dc48e add physical type annotation for interconnects and inference 2020-01-28 21:59:10 -07:00
tangxifan bb7fa2af77 add pb interconnect binding to circuit model 2020-01-28 17:04:10 -07:00
tangxifan 1651c9ca18 add binding between physical pb_type and circuit models 2020-01-28 16:03:02 -07:00
tangxifan a4a84ca35b add check codes for physical pb_type and port annotation 2020-01-28 15:27:00 -07:00
tangxifan 5d9850c2eb move pb_type annotation to independent source files as they are getting large 2020-01-28 15:13:14 -07:00
tangxifan fdcc04cca8 add physical pb_type inference 2020-01-28 14:55:47 -07:00
tangxifan caeb0bfff8 add physical pb_type binding for explicit annotations 2020-01-28 14:27:35 -07:00
tangxifan 82f71e82e8 add check codes for physical mode annotation for pb_types 2020-01-27 21:15:32 -07:00
tangxifan f99dd4c261 debugged pb_type physical mode annotation 2020-01-27 20:40:18 -07:00
tangxifan b8c504f574 Do not allow vpr to free everything when it is done. So that we can have access to their device data 2020-01-27 19:49:05 -07:00
tangxifan df056f5d70 openfpga shell will stay in interactive mode after executing a script 2020-01-27 17:56:24 -07:00
tangxifan 5ecb771673 debugging the annotation to physical mode of pb_types 2020-01-27 17:43:22 -07:00
tangxifan a6fbbce33e start developing the openfpga arch binding to vpr 2020-01-27 15:31:12 -07:00
tangxifan 01c80b9126 add sample architecture to be used for Openfpga 2020-01-27 13:39:13 -07:00
tangxifan 2e41138633 use a micro benchmark for vpr quick-run 2020-01-26 17:56:22 -07:00
tangxifan 93ab4b8dd2 add test case for openfpga shell 2020-01-26 17:30:46 -07:00
tangxifan 5039af2c2f update title page 2020-01-24 17:00:53 -07:00
tangxifan a7a1fe8a74 simplify openfpga title page and add command dependency on read_arch and write_arch 2020-01-24 16:57:14 -07:00
tangxifan d1725de606 add ctags script to index openfpga source files 2020-01-24 10:15:16 -07:00
tangxifan 655f84b00e add write_openfpga_arch command to openfpga shell 2020-01-23 20:58:15 -07:00
tangxifan a03f8aa346 add profiling for read arch 2020-01-23 20:12:30 -07:00
tangxifan cdb3b6de46 add read_openfpga_arch to OpenFPGA shell 2020-01-23 19:10:53 -07:00
tangxifan e69aa5ba30 change type casting for vpr macro 2020-01-23 14:57:53 -07:00
tangxifan 3cb16a2279 move basic commands to separated CXX files 2020-01-23 14:42:49 -07:00
tangxifan ba207ee5a5 start split workload from the main.cpp in openfpga 2020-01-23 13:24:35 -07:00
tangxifan 7909a1ad82 update title for openfpga shell 2020-01-22 20:29:57 -07:00
tangxifan 523f9ac391 start implement openfpga shell and use vpr as a macro 2020-01-22 20:20:10 -07:00