Commit Graph

4598 Commits

Author SHA1 Message Date
tangxifan 22e71f5847 Add rotate one side of switch block functionality 2019-05-25 22:48:07 -06:00
tangxifan 858a323228 Add more support for rotating Switch Blocks 2019-05-25 21:26:35 -06:00
tangxifan 2eab0b1c1c update unique_mirror search algorithm for Switch Blocks 2019-05-25 19:54:15 -06:00
tangxifan d3eae80e64 implemented an native way in finding rotable Switch blocks 2019-05-25 19:37:18 -06:00
tangxifan ae0248fbc6 debugging SwitchBlock rotating 2019-05-24 23:10:30 -06:00
tangxifan 9adc2945c8 add rotate functionality for RRSwitchBlock 2019-05-24 21:40:16 -06:00
tangxifan 02b48d036d clean warnings 2019-05-24 16:48:08 -06:00
tangxifan 2c46da6888 clean-up warnings Verilog routing generator 2019-05-24 16:29:17 -06:00
tangxifan 27b996337a fixed a critical bug in Compact Verilog generation for SB/CBs 2019-05-24 16:14:46 -06:00
tangxifan 1ade1f1d3f update SDC generator disabled_unused_mux by using RRSwitchBlock 2019-05-24 15:42:00 -06:00
tangxifan f27b88db8d Use RRChan in SDC generator to replace old data structures 2019-05-24 15:34:56 -06:00
tangxifan 27c234711e clean up warnings in SDC pb_type generator 2019-05-24 15:23:38 -06:00
tangxifan 924136e7a2 Clean warnings in SDC generator and use RRSwitchBlock to replace old data structure sb_info 2019-05-24 15:10:08 -06:00
tangxifan 994b90ae53 updated report_timing for using RRSwitchBlock 2019-05-24 14:25:51 -06:00
tangxifan eef1312325 updated bitstream to use new RRSwitchBlock as well as the report timing engine 2019-05-24 12:54:10 -06:00
tangxifan 5de38f023c Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-23 21:53:16 -06:00
tangxifan 8f4f590ff9 update Verilog compact_netlist outputter with RRSwitchBlock classes 2019-05-23 21:52:12 -06:00
AurelienUoU d3f0ab59c2 Remove -power token until option is fixed 2019-05-23 19:26:25 -06:00
AurelienUoU 3811c18953 Correct syntax error in tokens of regression_fpga_flow.sh 2019-05-23 18:33:47 -06:00
AurelienUoU 1018134726 Update yosys to latest version + add simulation in fpga_flow 2019-05-23 17:55:49 -06:00
tangxifan ee1a24d4ba Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-23 17:38:35 -06:00
tangxifan ea8c36ce6e upgrade Verilog SB generator using the RRSwitchBlock 2019-05-23 17:37:39 -06:00
AurelienUoU 555570c15e Update Yosys from version 0.7 to version 0.8 2019-05-23 16:03:08 -06:00
tangxifan ec70bcee99 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-22 22:05:46 -06:00
tangxifan 4aab93b729 update class rr_switch_block and be ready for updating the downstream verilog generator 2019-05-22 22:04:31 -06:00
AurelienUoU 2b04376209 Correct blif clock bame issue in fpga_flow and reload original MCNC benchmarks 2019-05-22 13:44:48 -06:00
tangxifan 502344b13a add missing files 2019-05-22 12:35:12 -06:00
tangxifan efbc454cdd Add Class for RRSwtichBlock and plug-in to replace the old t_sb 2019-05-22 12:34:06 -06:00
AurelienUoU b4c97f86a3 Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches 2019-05-21 17:24:06 -06:00
tangxifan d10e05f5cc Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-21 12:16:33 -06:00
tangxifan ec3b4c86c4 update file organization and be ready for SB/CB class 2019-05-21 12:15:38 -06:00
AurelienUoU 7192ca212d Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-21 10:36:30 -06:00
AurelienUoU 199cd99b23 Add dummy clock name in ace2 commands 2019-05-21 10:35:12 -06:00
tangxifan 8186d6dd11 reorganize files and clean some warnings 2019-05-21 10:17:54 -06:00
tangxifan b185a17359 add routing_channel unique module generation 2019-05-20 22:33:17 -06:00
giacomin ceee28226e Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-20 16:47:07 -06:00
giacomin 8b520349e7 fixed a bug for rram based fpga when using explicit verilog port mapping 2019-05-20 16:44:47 -06:00
AurelienUoU 2392d11790 Add debug command to understandn travis issue with ace 2019-05-20 16:06:37 -06:00
AurelienUoU becb90cd16 Correct syntax error in ace2 log file generation 2019-05-20 13:56:50 -06:00
AurelienUoU fbebb45bf2 Path correction in config file 2019-05-20 11:13:30 -06:00
AurelienUoU 82c76a2c39 Test removing the shell specification in fpga_flow.pl 2019-05-20 10:35:33 -06:00
AurelienUoU 43a64c26e8 Change tcsh to csh in fpga_flow.pl -> tcsh not found by travis 2019-05-20 09:44:38 -06:00
AurelienUoU af01ca4a0d Path correction in travis regression test 2019-05-20 08:53:19 -06:00
AurelienUoU 17ad905b14 Update flow and allow netlist generation 2019-05-17 17:00:38 -06:00
AurelienUoU df8bb0db1a Add MCNC Benchmarks netlists generation to travis regression test 2019-05-17 15:22:04 -06:00
AurelienUoU 4f921b03da Add travis full path to avoid missing sources 2019-05-16 15:51:10 -06:00
AurelienUoU 9b28b303b4 Correction of path error 2019-05-16 15:05:34 -06:00
AurelienUoU f31339bb5c Correctly instantiate script variables 2019-05-16 14:30:16 -06:00
AurelienUoU 8c9820e7ee Test without Verilog verification to se impact in building errors 2019-05-16 09:48:06 -06:00
AurelienUoU c4ccff4562 Move Verilog test in another script to avoid false failure 2019-05-16 09:05:30 -06:00