Commit Graph

1640 Commits

Author SHA1 Message Date
tangxifan ef11482a95 fix dependency error in pack_types header file 2020-02-18 11:36:16 -07:00
tangxifan 6060440b97 fine tuning for the verbose output 2020-02-17 21:14:15 -07:00
tangxifan 409b3f6896 add lb_rr_graph builder for the refactored version 2020-02-17 21:11:56 -07:00
tangxifan 8e97443410 start working on repack 2020-02-17 17:57:43 -07:00
tangxifan 62e4f14e30 add lb_rr_graph to device annotation 2020-02-17 17:26:27 -07:00
tangxifan 6c69b52ded Add missing file 2020-02-17 17:11:29 -07:00
tangxifan 92076c1460 refactored lb_rr_graph in the same principle of RRGraph object 2020-02-17 16:59:24 -07:00
tangxifan 60f40a9657 use constant module manager as much as possible in Verilog writer 2020-02-16 16:35:26 -07:00
tangxifan 11775c370b bring FPGA top module verilog writer online. Fabric Verilog generator done 2020-02-16 16:18:14 -07:00
tangxifan e37ac8a098 add grid module Verilog writer 2020-02-16 16:04:41 -07:00
tangxifan c20caa1fa3 routing module Verilog writer is online 2020-02-16 14:47:54 -07:00
tangxifan c6c3ef71f3 adapt all the Verilog submodule writers and bring it onlien 2020-02-16 13:35:18 -07:00
tangxifan 99c3712b6f adapt Verilog wire module writer 2020-02-16 12:59:37 -07:00
tangxifan 5cc68b0730 adapt LUT Verilog writer 2020-02-16 12:45:58 -07:00
tangxifan 105ccabecc adapt memroy writer for verilog 2020-02-16 12:41:43 -07:00
tangxifan c9d8120ae0 adapt Verilog mux writer 2020-02-16 12:35:41 -07:00
tangxifan a88c4bc954 add decode utils to libopenfpga and adapt local decoder writer in Verilog 2020-02-16 12:21:59 -07:00
tangxifan 3efd1a2a6d print verilog module writer online 2020-02-16 12:04:03 -07:00
tangxifan cf34339e96 adapt essential gates for submodule generation 2020-02-16 11:57:19 -07:00
tangxifan 2eba882332 put verilog submodules online. ready to bring the how submodule writer online 2020-02-16 11:41:20 -07:00
tangxifan 4cb61e2138 bring preprocessing flag Verilog netlists online 2020-02-16 00:03:24 -07:00
tangxifan 0d5292ad0d adapt verilog writer utils 2020-02-15 23:26:59 -07:00
tangxifan bf54be3d00 add option data structure for FPGA Verilog 2020-02-15 21:39:47 -07:00
tangxifan da79ef687c add missing files 2020-02-15 20:54:37 -07:00
tangxifan 8b0df8632c bring fpga verilog create directory online 2020-02-15 20:38:45 -07:00
tangxifan 622c7826d1 start transplanting fpga_verilog 2020-02-15 15:03:00 -07:00
tangxifan 85627dc128 put build top module online 2020-02-15 14:13:32 -07:00
tangxifan 539f13720a tile direct supports inter-column/inter-row direct connections 2020-02-15 13:42:53 -07:00
tangxifan 213c611c0b add tile direct builder 2020-02-14 22:21:32 -07:00
tangxifan 7e86cf1079 add tile direct data structure 2020-02-14 19:11:49 -07:00
tangxifan 59c13550e0 add direct annotation with inter-column/row syntax 2020-02-14 17:40:59 -07:00
tangxifan c855ab24f5 put build top module memory connections online 2020-02-14 11:07:04 -07:00
tangxifan 9dc9c2c9f7 add build top module connection functions 2020-02-14 10:45:24 -07:00
tangxifan 36179b6ced start moving top-module builder. Now adapt the utils 2020-02-14 10:00:24 -07:00
tangxifan afe8278670 put routing module builder online 2020-02-13 17:35:29 -07:00
tangxifan cf440f92d3 put routing module builder util function online 2020-02-13 16:05:23 -07:00
tangxifan 89086ed080 add verbose output to build grid module 2020-02-13 15:38:26 -07:00
tangxifan 072965cd64 make grid module builder online; basic support on physical tiles 2020-02-13 15:27:16 -07:00
tangxifan 59d579425e add utils for duplicate pins in grid module builder 2020-02-12 20:48:07 -07:00
tangxifan 895d5b5a0a add utils for grid module builder 2020-02-12 20:25:05 -07:00
tangxifan 002c2795fe add memory module builder 2020-02-12 20:06:38 -07:00
tangxifan 8e381f0581 add wire module builder 2020-02-12 19:57:15 -07:00
tangxifan e842150cc5 add lut module builder 2020-02-12 19:52:41 -07:00
tangxifan fddd3c9463 add mux module builder 2020-02-12 19:45:14 -07:00
tangxifan ea7d879b4f add decoder module builder 2020-02-12 18:28:50 -07:00
tangxifan f11832b8cf start integrating module graph builder 2020-02-12 17:53:23 -07:00
tangxifan 13fadd0f91 move compact routing hierarchy to build_fabric command 2020-02-12 15:49:47 -07:00
tangxifan df3ae60954 add default configurable memory model set-up when reading openfpga architecture XML 2020-02-12 15:19:40 -07:00
tangxifan c78d3e9af1 add mux library builder 2020-02-12 14:58:23 -07:00
tangxifan ce63b1cc62 add circuit model binding for direct connections and enhance model type checking 2020-02-12 11:40:20 -07:00