tangxifan
|
cffdebd912
|
bug fixed for the tileable RR graph generator for heterogeneous blocks
|
2019-07-11 21:02:09 -06:00 |
|
tangxifan
|
75ff2e904e
|
Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing
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2019-07-11 19:41:24 -06:00 |
|
tangxifan
|
e633e3d17b
|
update fpga_flow scripts to support vpr_only flow
|
2019-07-11 19:40:58 -06:00 |
Baudouin Chauviere
|
c9b84f61c9
|
Hot fix
|
2019-07-11 17:39:02 -06:00 |
|
Baudouin Chauviere
|
d0cd5a2bc1
|
Hot fix
|
2019-07-11 17:27:31 -06:00 |
|
tangxifan
|
9c203ca4d2
|
bug fixing in SDC generator
|
2019-07-11 17:10:08 -06:00 |
AurelienUoU
|
1848771e54
|
Add explicit mapping option into fpga_flow
|
2019-07-11 14:44:30 -06:00 |
|
Baudouin Chauviere
|
f4be375637
|
Latest version explicit
|
2019-07-11 14:33:56 -06:00 |
|
AurelienUoU
|
ad0b4b3acd
|
Merge remote-tracking branch 'origin/dev' into documentation
|
2019-07-11 10:15:26 -06:00 |
|
AurelienUoU
|
346b6f3e8e
|
Update docker part in building.md
|
2019-07-11 10:13:55 -06:00 |
|
AurelienUoU
|
c556b85d66
|
Update docker instruction
|
2019-07-11 10:10:30 -06:00 |
|
tangxifan
|
31749fe62b
|
fix bugs in fpga_flow.pl
|
2019-07-10 21:12:00 -06:00 |
|
AurelienUoU
|
3cd214ada2
|
tuto flow v2.1
|
2019-07-10 16:14:38 -06:00 |
|
AurelienUoU
|
db9c4be963
|
Tuto flow v2
|
2019-07-10 16:00:22 -06:00 |
|
AurelienUoU
|
9d7ae2f6ec
|
Update tutorial flow demo draft 6
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2019-07-10 15:42:31 -06:00 |
|
tangxifan
|
a90316e9f4
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-10 15:13:46 -06:00 |
|
tangxifan
|
acee0161c7
|
Merge branch 'tileable_routing' into dev
|
2019-07-10 15:13:24 -06:00 |
|
tangxifan
|
206fc84a0e
|
minor fix in fpga_flow
|
2019-07-10 15:12:51 -06:00 |
|
AurelienUoU
|
a47711203c
|
Tuto update draft 5
|
2019-07-10 14:59:03 -06:00 |
|
Baudouin Chauviere
|
6441f2ebe7
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-10 14:16:55 -06:00 |
|
Baudouin Chauviere
|
0a978db866
|
Fix regression test
|
2019-07-10 14:16:34 -06:00 |
|
tangxifan
|
b7f9831bd2
|
add statistics for unique GSBs
|
2019-07-10 13:08:03 -06:00 |
|
AurelienUoU
|
422ede7610
|
Update tutorial draft 4
|
2019-07-10 12:17:07 -06:00 |
|
tangxifan
|
c6a4d29ed8
|
Merge branch 'tileable_routing' into dev
|
2019-07-10 12:05:43 -06:00 |
|
AurelienUoU
|
cb782a0e9f
|
Draft 3
|
2019-07-10 11:00:36 -06:00 |
|
AurelienUoU
|
905293820f
|
Draft2
|
2019-07-10 10:37:05 -06:00 |
|
AurelienUoU
|
20ce020eb6
|
Tutorial rewrite draft 1
|
2019-07-10 10:03:30 -06:00 |
|
tangxifan
|
57ae5dbbec
|
bug fixing for rectangle FPGA sizes
|
2019-07-09 20:47:52 -06:00 |
|
tangxifan
|
edfe3144c3
|
update profiling, found where runtime is lost
|
2019-07-09 20:28:01 -06:00 |
|
tangxifan
|
737cc2874f
|
Merge branch 'tileable_routing' into dev
|
2019-07-09 17:42:44 -06:00 |
|
tangxifan
|
65f696c1d7
|
fix critical bugs in rectangle floorplan
|
2019-07-09 17:41:20 -06:00 |
|
Baudouin Chauviere
|
4ca0967453
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-09 14:35:51 -06:00 |
|
Baudouin Chauviere
|
792ba23f4f
|
Correction pre-merge
|
2019-07-09 14:34:34 -06:00 |
|
AurelienUoU
|
e86c9b9bfc
|
Update tutorial, readme and docker
|
2019-07-09 14:28:14 -06:00 |
|
AurelienUoU
|
0da9e50b20
|
Modify readme
|
2019-07-09 11:58:39 -06:00 |
|
Baudouin Chauviere
|
589f58b55e
|
Regression test succeeded
|
2019-07-09 09:18:06 -06:00 |
|
Baudouin Chauviere
|
25f5bc7792
|
Latest version, not stable yet but close
|
2019-07-09 08:34:01 -06:00 |
|
tangxifan
|
5d5e09fcdb
|
minor fix in trying to accelerate the unique routing functions
|
2019-07-08 17:12:36 -06:00 |
|
AurelienUoU
|
c3b34a6297
|
Update font in tutorial
|
2019-07-08 16:26:29 -06:00 |
|
AurelienUoU
|
8366f9e7b7
|
Update tutorial
|
2019-07-08 16:18:08 -06:00 |
|
AurelienUoU
|
f1ccf85bb9
|
Update tutorial -> fpga_flow explanation
|
2019-07-08 11:51:04 -06:00 |
|
AurelienUoU
|
9f16bb5998
|
Synthax correction 2 -> new line
|
2019-07-08 10:36:58 -06:00 |
|
AurelienUoU
|
c1ae3059c4
|
Correct synthax error
|
2019-07-08 10:32:39 -06:00 |
|
AurelienUoU
|
b2717abc3e
|
Replace obsolete example folder and start tutorial
|
2019-07-08 10:30:26 -06:00 |
|
Baudouin Chauviere
|
df0a3d23a3
|
Correction top module
|
2019-07-08 10:23:14 -06:00 |
|
Baudouin Chauviere
|
ae05c553d5
|
Top module done
|
2019-07-08 09:48:33 -06:00 |
|
tangxifan
|
fb064daded
|
Merge branch 'tileable_routing' into dev
|
2019-07-05 21:15:59 -06:00 |
|
tangxifan
|
76fefdb876
|
bug fixing in Fc_in and be serious in the performance of rr_graph
|
2019-07-05 16:23:15 -06:00 |
|
tangxifan
|
c62762ce59
|
bug fixing in assign ipins to tracks using Fc_in
|
2019-07-05 13:42:22 -06:00 |
|
AurelienUoU
|
df53f6da2c
|
Updates FPGA-Verilog command lines
|
2019-07-05 13:41:34 -06:00 |