tangxifan
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8853370c60
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[Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file
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2021-02-04 20:20:10 -07:00 |
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tangxifan
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d3397f6936
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[Script] Remove activity from bitstream setting example script
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2021-02-02 09:25:36 -07:00 |
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tangxifan
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7f14dfbe87
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[Script] Add example script to use bitstream setting
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2021-02-02 09:18:08 -07:00 |
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tangxifan
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8b74947737
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[Script] Now multi-clock openfpga shell script no longer needs activity file
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2021-01-29 11:40:33 -07:00 |
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tangxifan
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3fdd5ae8b3
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[Script] Use pin constraints in template script
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2021-01-19 17:42:25 -07:00 |
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tangxifan
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12e0efd03e
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[Script] Add an example openfpga script to use repack design constraints
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2021-01-17 10:33:56 -07:00 |
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tangxifan
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c5a2027f36
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[Flow] Use implicit port mapping to avoid renaming problem between yosys and VPR
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2021-01-13 15:41:48 -07:00 |
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tangxifan
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18d2a8ce19
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[Flow] Add new script for fixed device layout using global tile clock
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2021-01-10 11:08:02 -07:00 |
Lalit Sharma
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2484721a45
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Updating write_verilog_testbench by removing option explicit_port_mapping
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2020-12-22 22:17:50 -08:00 |
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tangxifan
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fd80cacaa3
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[Flow] Add example script for behaviorial verilog generation
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2020-11-22 21:14:10 -07:00 |
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tangxifan
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655da9f3d0
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |