tangxifan
|
999c364b25
|
added XML parsing for circuit model ports
|
2020-01-15 17:29:49 -07:00 |
|
tangxifan
|
c20e1d48d2
|
added XML parsing for pass-gate-logic in circuit models
|
2020-01-15 15:49:02 -07:00 |
|
tangxifan
|
a9b122d584
|
add XML parsing for buffer models in circuit library
|
2020-01-15 15:27:49 -07:00 |
|
tangxifan
|
35d6c9661b
|
Finish the first version of XML parser for design technology of circuit models
|
2020-01-14 16:24:27 -07:00 |
|
tangxifan
|
5937ffc809
|
add XML parsing for buffer/pass-gate-logic -related properties
|
2020-01-14 15:44:24 -07:00 |
|
tangxifan
|
56113e1aab
|
adding XML parsing for design tech of circuit model
|
2020-01-14 14:10:00 -07:00 |
|
tangxifan
|
2692d0fc35
|
adding XML parsing for SPICE and Verilog netlist for each circuit model
|
2020-01-14 08:45:27 -07:00 |
|
tangxifan
|
82d83ddceb
|
reorganized the read XML openfpga arch
|
2020-01-14 08:33:48 -07:00 |
|
tangxifan
|
ca3ca14cc7
|
fixed bugs in XML when parsing circuit model types
|
2020-01-13 21:52:13 -07:00 |
|
tangxifan
|
db503ffebf
|
add openfpga read xml executable and start min unit test
|
2020-01-13 21:05:58 -07:00 |
|
tangxifan
|
d6c69ea7c6
|
developing XML parser for circuit model name and type
|
2020-01-12 23:45:51 -07:00 |
|
tangxifan
|
e2f641fdb3
|
add example architecture for openfpga and developing XML parser
|
2020-01-12 22:39:38 -07:00 |
|
tangxifan
|
2e986608ba
|
initial commit on parser for reading openfpga arch xml
|
2020-01-12 21:33:28 -07:00 |
|
tangxifan
|
5dea648be6
|
add missing CMakeList for libarchopenfpga
|
2020-01-12 18:15:36 -07:00 |
|
tangxifan
|
48ecb6e48b
|
immigrate XML parser for circuit_lib to library readarchopenfpga
|
2020-01-12 18:11:00 -07:00 |