riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
4,468 Commits 70 Branches 8 Tags 105 MiB
Commit Graph

4468 Commits

Author SHA1 Message Date
tangxifan 3146d2484f [Doc] Update documentation on the WLR definition for circuit model 2021-09-20 17:21:33 -07:00
tangxifan d36d1ebee2 [HDL] Temporarily disable WLR func in primitive HDL modeling 2021-09-20 17:07:51 -07:00
tangxifan c84c0d4a3f [FPGA-Verilog] Upgrade fpga-verilog to support decoders with WLR 2021-09-20 17:07:26 -07:00
tangxifan 36a4da863c [Engine] Support WLR port in OpenFPGA architecture file and fabric generator 2021-09-20 16:05:36 -07:00
tangxifan 0450d57d82 [Arch] Fixed critical bugs in the OpenFPGA architecture file for QL memory bank with WLR 2021-09-20 16:05:01 -07:00
tangxifan 3f6ac41868 [Test] Deploy the WLR test to the basic regression tests 2021-09-20 11:21:58 -07:00
tangxifan 60fc3ab36c [Test] Added a new test case for the WLR memory bank 2021-09-20 11:20:36 -07:00
tangxifan 5c1c428ea5 [HDL] Updated cell library with the SRAM cell with Read Enable signal 2021-09-20 11:13:36 -07:00
tangxifan cd2978a434 [Arch] Added a new architecture example which shows how to use the memory bank with readback functionality 2021-09-20 11:13:02 -07:00
slt b867db815f
Update fpgaflow_default_tool_path.conf 
Update regex for VPR
 2021-09-17 14:02:26 +08:00
tangxifan 6d151527ca
Merge pull request #8 from RapidSilicon/phy_mem_bank 
Reduce Unique BL/WLs for Top-level Module in Physical Design Friendly Memory Bank
 2021-09-15 16:07:22 -07:00
tangxifan 2e45a6143b [Engine] Fix a critical bug which causes flatten memory tests failed 2021-09-15 15:11:58 -07:00
tangxifan f2aa31ddb1 [FPGA-Bitstream] Fix the bug which causes bitstream wrong for QL memory bank 2021-09-15 13:45:30 -07:00
tangxifan 061952b7fa [Engine] Bug fix in computing local WLs for GRID/CB/SB 2021-09-15 11:51:00 -07:00
tangxifan 26b1e48723 [Engine] Merge BL/WLs in the Grid/CB/SB modules 2021-09-15 11:27:55 -07:00
tangxifan d0e60c0697
Merge pull request #6 from RapidSilicon/phy_mem_bank 
Alpha Version of New Configuration Protocol: Physical Design Friendly Memory Bank
 2021-09-10 21:18:32 -07:00
tangxifan 4af6413c97 [Engine] Fixed a critical bug on WL arrangement; Previously we always consider squart of a local tile. Now we apply global optimization where the number of WLs are determined by the max. number of BLs per column 2021-09-10 17:03:44 -07:00
tangxifan 73d21c9730 [Doc] Update doc about how to use the QuickLogic memory bank 2021-09-10 15:30:37 -07:00
tangxifan ba1e277dc9 [Engine] Fix a few bugs in the BL/WL arrangement and now bitstream generator is working fine 2021-09-10 15:05:46 -07:00
tangxifan 35c7b09888 [Engine] Bug fix for mistakes in calculating number of BLs/WLs for QL memory bank 2021-09-09 15:23:29 -07:00
tangxifan b787c4e100 [Engine] Register QL memory bank as a legal protocol 2021-09-09 15:06:51 -07:00
tangxifan 81a2ad58df [Test] Deploy the ql memory bank test case to basic regression tests (run on CI) 2021-09-09 13:48:30 -07:00
tangxifan b82cfdf555 [Test] Add the QL memory bank test to regression test cases 2021-09-09 09:29:21 -07:00
tangxifan 6be3c64f1c [Arch] Add an example architecture using the physical design friendly memory bank organization 2021-09-09 09:22:27 -07:00
tangxifan 1aac3197eb [FPGA-Verilog] Upgrade testbench generator to support QL memory bank 2021-09-05 21:38:00 -07:00
tangxifan 6f09f5f7ad [FPGA-Bitstream] Upgrade bitstream generator to support QL memory bank 2021-09-05 21:25:58 -07:00
tangxifan 1085e468e2 [Engine] Move most utilized functions for memory bank configuration protocol to a separated source file 2021-09-05 20:45:56 -07:00
tangxifan 475ce2c6d9 [Engine] Upgrade fabric generator in support QL memory bank connections 2021-09-05 17:49:01 -07:00
tangxifan ed80d6b3f4 [Engine] Place QL memory bank source codes in a separated source file so that integration to OpenFPGA open-source version is easier 2021-09-05 13:23:38 -07:00
tangxifan cf2e479d18 [Engine] Refactor the TopModuleNumConfigBits data structure 2021-09-05 12:01:38 -07:00
tangxifan f75456e304 [Engine] Update BL/WL estimation function for QL memory bank protocol 2021-09-05 11:53:33 -07:00
tangxifan 30feb78469
Merge pull request #364 from lnis-uofu/tutorials 
Tutorials
 2021-09-04 19:07:46 -07:00
tangxifan 5759f5f35b [Engine] Start developing QL memory bank: upgrade infrastructures of fabric builder 2021-09-03 17:55:23 -07:00
tangxifan c206c4e95e
Merge pull request #5 from RapidSilicon/upstream_sync 
Synchronize to upstream OpenFPGA
 2021-09-02 20:50:43 -07:00
tangxifan 5d22de7ac9 [Yosys] Revert to an older version of yosys that works in regresstion tests 2021-09-02 20:00:47 -07:00
tangxifan d37cfe96bd [Git] Remove RTL benchmarks submodule 2021-09-02 16:51:07 -07:00
tangxifan a2a5d6b97b [Git] Removed RTL benchmarks now as it is failing CI; Should consider bring it back sometime 2021-09-02 16:46:35 -07:00
tangxifan cc546cdedc [CI] Enable github actions 2021-09-02 16:42:24 -07:00
tangxifan 6adf439081 Merge remote-tracking branch 'upstream/master' 2021-09-01 14:19:00 -07:00
tangxifan 801b91f776
Merge branch 'master' into tutorials 2021-08-31 17:17:40 -07:00
Andrew Pond 3c041b6012
Merge pull request #363 from lnis-uofu/compilation_readme 
Update compile.rst
 2021-08-17 11:08:14 -06:00
Andrew Pond 7537118843
Merge branch 'master' into compilation_readme 2021-08-17 10:19:31 -06:00
ANDREW HARRIS POND 1c09b8c3e0 fixed python instruction 2021-08-17 10:18:51 -06:00
ganeshgore d14a7f74f0
Merge pull request #366 from WRansohoff/accept_absolute_task_paths 
Accept absolute project paths in the 'run_fpga_task.py' script
 2021-08-13 11:17:33 -06:00
Will c31c1d8b04 Accept absolute project paths as inputs to the 'run_fpga_task.py' script. 2021-08-13 11:08:09 -04:00
bbleaptrot 814d290463
Merge branch 'master' into tutorials 2021-08-05 10:24:34 -06:00
bbleaptrot c867c7e628
Update index to include FAQ page 2021-07-28 10:14:31 -06:00
bbleaptrot 2bb76e4a82
Update to include suggested changes 2021-07-28 10:13:25 -06:00
bbleaptrot 17d3fb5d5e
Add FAQ to source folder to go along in appendix 2021-07-28 10:10:17 -06:00
Andrew Pond a8a8c25a21
Update compile.rst 2021-07-26 15:18:23 -06:00