9a8c7b391a
Add process for modelsim script autogeneration
2018-12-05 09:20:47 -07:00
75d64db0f9
Add verilog header sub_module.v file generation
2018-12-04 18:42:47 -07:00
8ac566ecc0
Add timing and initialization for simulation
2018-12-04 17:32:09 -07:00
70751551b5
fix a bug in wired LUT support
2018-11-30 21:33:31 -07:00
e223868df8
fix bugs for wired LUTs
2018-11-27 12:46:30 -07:00
de2bc18bbb
bugs fixed for shift register benchmark
2018-11-26 16:58:45 -07:00
9611576d6a
Update on the examples to respect the new syntax
2018-11-19 15:50:29 -07:00
861c449606
support wired LUT in FPGA-SPICE and FPGA-Verilog
2018-11-15 15:57:49 -07:00
f7d7a056da
Modification of the fpga_spice_utils
2018-11-15 14:11:55 -07:00
c81d00bb51
Correction of the double free bug
2018-11-15 13:55:16 -07:00
e0c2fc2c8a
Documentation_code&example_update
2018-10-12 15:50:09 -06:00
c67ba5f58a
clean up codes
2018-09-27 14:26:08 -06:00
31c3eba111
ReadMe modifications to add the beginning of the FPGA-SPICE tutorial
...
Modifications on the addresses aswell and the different commands when they were not working.
To do still:
-create a script to change the addresses when needed
-continue the tutorial
2018-09-27 09:33:39 -06:00
681cca99a4
fix a bug in tapbuf
2018-09-21 19:00:22 -06:00
d683134b12
rename customized vpr7 to vpr7 XML to Production
2018-09-17 23:10:45 -06:00
Aur??Lien ALACCHI
tangxifan
Baudouin Chauviere
Baudouin Chauviere
Aurelien Alacchi