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OpenFPGA
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101 Commits

Author SHA1 Message Date
tangxifan 6e1d49d74e start to support direct mapping to MUX2 standard cells 2019-07-17 07:54:23 -06:00
Baudouin Chauviere 65122d04b3 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2019-07-16 13:37:21 -06:00
AurelienUoU 509c1d2c80 Link path correction 2019-07-16 13:13:58 -06:00
Baudouin Chauviere 69014704ef Explicit verilog final push 2019-07-16 13:13:30 -06:00
AurelienUoU 3d079c9421 Add folder creation in tuto_fpga_flow.sh to ease the use 2019-07-16 07:20:21 -06:00
AurelienUoU b810b5cab9 fpga_flow bug fix + upload k8 architecture 2019-07-16 07:04:45 -06:00
AurelienUoU 35e1962732 Merge branch 'dev' into documentation 2019-07-15 21:19:26 -06:00
AurelienUoU 19ccbce9d0 Rename option to use circuit_model rather than spice_model 2019-07-12 16:18:28 -06:00
AurelienUoU e65cf9f5fd Update ERI-demo 2019-07-12 08:55:19 -06:00
tangxifan e633e3d17b update fpga_flow scripts to support vpr_only flow 2019-07-11 19:40:58 -06:00
tangxifan 9c203ca4d2 bug fixing in SDC generator 2019-07-11 17:10:08 -06:00
AurelienUoU 1848771e54 Add explicit mapping option into fpga_flow 2019-07-11 14:44:30 -06:00
AurelienUoU ad0b4b3acd Merge remote-tracking branch 'origin/dev' into documentation 2019-07-11 10:15:26 -06:00
tangxifan 31749fe62b fix bugs in fpga_flow.pl 2019-07-10 21:12:00 -06:00
AurelienUoU 9d7ae2f6ec Update tutorial flow demo draft 6 2019-07-10 15:42:31 -06:00
tangxifan acee0161c7 Merge branch 'tileable_routing' into dev 2019-07-10 15:13:24 -06:00
tangxifan 206fc84a0e minor fix in fpga_flow 2019-07-10 15:12:51 -06:00
AurelienUoU a47711203c Tuto update draft 5 2019-07-10 14:59:03 -06:00
AurelienUoU 905293820f Draft2 2019-07-10 10:37:05 -06:00
AurelienUoU 20ce020eb6 Tutorial rewrite draft 1 2019-07-10 10:03:30 -06:00
Baudouin Chauviere 4ca0967453 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2019-07-09 14:35:51 -06:00
Baudouin Chauviere 792ba23f4f Correction pre-merge 2019-07-09 14:34:34 -06:00
Baudouin Chauviere 589f58b55e Regression test succeeded 2019-07-09 09:18:06 -06:00
AurelienUoU 8366f9e7b7 Update tutorial 2019-07-08 16:18:08 -06:00
AurelienUoU b4a78abc04 Update doc 
Merge remote-tracking branch 'origin/heterogeneous' into dev
 2019-07-05 12:25:37 -06:00
tangxifan c8ceb8f7d5 update fpga_flow.pl 2019-07-04 12:23:11 -06:00
tangxifan 5a50fa84d1 keep updating fpga_flow.pl to use system call 2019-07-03 22:57:43 -06:00
tangxifan 6b894640c7 bug fixing in fpga_flow.pl 2019-07-03 14:59:05 -06:00
tangxifan d5137eb424 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing 2019-07-03 14:31:18 -06:00
tangxifan 5195faab8b Merge branch 'dev' into tileable_routing 2019-07-03 14:30:39 -06:00
tangxifan 4f3cb0bdf3 added tileable routing chanW adaption to fixed W router 2019-07-03 14:29:50 -06:00
Ganesh Gore 443a73954f Removed all local files 
+ Removed local configurations and scripts from previous commit
 2019-07-03 14:26:06 -06:00
tangxifan c9743e84da Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2019-07-03 14:12:47 -06:00
tangxifan a539c6a2a7 bug fixing in fpga_flow.pl 2019-07-03 14:11:14 -06:00
Ganesh Gore 57ad71438b Merging ganesh_dev to dev 
- Added spice_tool option in fpga_flow
- Some local customization
 2019-07-03 13:39:52 -06:00
AurelienUoU e13c703709 Upload recent commit 
Merge remote-tracking branch 'origin/dev' into heterogeneous
 2019-07-03 13:09:34 -06:00
AurelienUoU 43e9d8afd1 Add compact routing hierarchy option in fpga_flow 2019-07-03 13:08:49 -06:00
Ganesh Gore 3c36a51011 Added 'rewrite_path_in_file' back to repository 2019-07-03 12:49:25 -06:00
Ganesh Gore 53486b8a89 Added 'spice_simulator_path' in fpga_flow 
added vpr_fpga_spice_simulator_path in fpga-flow script
 2019-07-03 12:30:56 -06:00
tangxifan 0c3e8bb70a add a new option to the router to enable conversion of route_chan_width to be tileable 2019-07-03 12:11:48 -06:00
tangxifan 02398818a9 update fpga_flow scripts to support matlab data format. Minor fix on rr_graph_area 2019-07-03 10:33:02 -06:00
tangxifan 4392c6bc3a bug fixing in fpga_flow scripts and add more print-out message for VPR 2019-07-02 15:34:59 -06:00
AurelienUoU 60f7ab0465 Start heterogeneous dev 2019-07-02 10:16:10 -06:00
Ganesh Gore 54f6ca2687 Added lattice benchmark settings 2019-07-01 11:07:23 -06:00
tangxifan c54f3905d5 fixed broken fpga flow 2019-06-28 13:07:04 -06:00
tangxifan 1332ba62e8 update tileable rr_graph generator to improve routability and also enable assoicated testing 2019-06-27 17:52:25 -06:00
tangxifan 4d3b5f12b4 fixed bugs for UNIVERSAL and WILTON switch blocks 2019-06-25 14:15:29 -06:00
AurelienUoU c76dbaac33 Update regression test avoiding overwritting files 2019-06-14 11:44:44 -06:00
tangxifan 0902d1e75a c++ string is not working, use char which is stable 2019-06-13 18:38:46 -06:00
AurelienUoU bf13c1f731 Add a script to create a new file with correct path rather than overwrite the existing 2019-06-11 14:28:58 -06:00