Commit Graph

35 Commits

Author SHA1 Message Date
tangxifan aebf7453d0 [Arch] Add architecture files with compatible I/O capacity with caravel SoC 2020-11-04 16:57:00 -07:00
tangxifan cf455df555 [Arch] Add architecture for bottom-right and top-left tile organization 2020-11-04 16:24:36 -07:00
tangxifan 46ca406f10 [Arch] Add a new vpr architecture with new tile organization 2020-11-04 16:20:01 -07:00
tangxifan 049ca14461 [Doc] Add new naming rules for vpr architecture files 2020-11-04 16:17:56 -07:00
tangxifan 3b49e6d090 [Arch] Patch embedded IO architecture by forcing only 1 pad per block 2020-11-02 15:39:31 -07:00
tangxifan a7e7fa2005 [Arch] Update arch with true embedded I/O definition 2020-11-02 13:29:40 -07:00
tangxifan 8c8190047f [Arch] Rename architecture files for embedded I/Os 2020-11-02 13:15:19 -07:00
tangxifan 795b30f76b [Arch] Add VPR architecture with partial pin equivalence 2020-11-02 11:54:25 -07:00
tangxifan 951a47b19c [Architecture] Add k4 series architecture using pattern-based local routing 2020-09-23 16:05:39 -06:00
tangxifan 70b8b02f74 [Architecture] Add vpr architecture for k4n4 with fracturable 32-bit multiplier 2020-09-22 15:32:11 -06:00
tangxifan 8a3934b749 [Architecture Add vpr architecture for k4n4 using multiple wire segments 2020-09-22 12:35:39 -06:00
tangxifan daf776b7b1 [Architecture] Add k4n4 architecture with bram block for basic tests 2020-09-22 12:22:32 -06:00
tangxifan 7a6f5a06f7 [Architecture] Add a k4n4 architecture with carry chain to quick test 2020-09-22 11:33:56 -06:00
tangxifan aa5f5fc7e0 [Architecture] Bring back pin equivalence for no local routing architecture 2020-09-21 22:22:39 -06:00
tangxifan a8a269aa82 [Architecture] Temporary patch for the no local routing architecture 2020-09-21 19:51:23 -06:00
tangxifan 7a57cc9cf4 [Architecture] A new device layout to k4n4 to test untileable architecture 2020-09-21 18:36:50 -06:00
tangxifan 2bbfcb5753 [Architecture] Add a new device layout to k4n4 for testing tileable routing 2020-09-21 18:34:31 -06:00
tangxifan e1c5947143 [Architecture] Add auto layout and fixed layout to architectures 2020-09-21 18:01:51 -06:00
tangxifan d7f8b3abad [Architecture] Add k4 N4 untilable architecture 2020-09-21 17:44:37 -06:00
tangxifan e9c0e90544 [Architecture] Add a VPR architectue using fracturable LUT4 2020-09-21 17:37:26 -06:00
tangxifan ca1bafc688 [OpenFPGA Architecture] Add full pin equivalence to full output crossbar architecture 2020-09-16 19:26:12 -06:00
tangxifan c22d8e2421 [Architecture] Bug fix in no local routing architecture 2020-09-16 18:07:52 -06:00
tangxifan f5b7ac6269 [OpenFPGA Architecture] Add a new architecture with no local routing 2020-09-16 18:04:55 -06:00
tangxifan 030d7f02f8 [OpenFPGA architecture] bug fix in the fully connected output crossbar architecture 2020-09-16 17:30:08 -06:00
tangxifan 3c0faf0021 [OpenFPGA Architecture] Add a new architecture with fully connected crossbar at CLB outputs 2020-09-16 17:27:24 -06:00
tangxifan 6c925dcded [regression test] Add more tests for thru channels and deploy to CI 2020-08-19 20:11:37 -06:00
tangxifan 881672d46a update thru channel arch for avoid buggy pin locations 2020-08-19 19:52:35 -06:00
tangxifan 3273f441fe bug fix in the flagship vpr arch 2020-08-19 15:23:20 -06:00
tangxifan d7efdf35b6 add custom pin location to the flagship vpr arch with frac mem and dsp 2020-08-19 11:15:25 -06:00
tangxifan 3ee4e10aa8 bug fix in the frac mem & DSP vpr arch 2020-08-18 17:25:45 -06:00
tangxifan f833e0ec66 add a flagship architecture using fracturable memory and dsp 2020-08-17 17:49:51 -06:00
tangxifan 1ca2829868 update readme for vpr architecture naming 2020-08-17 13:54:26 -06:00
tangxifan 534c609e17 add fixed layouts to a flagship architecture to test bitstream generation runtime 2020-07-28 11:51:50 -06:00
tangxifan f754c8af06 use k6_n10 architecture to reduce CI runtime 2020-07-22 13:45:55 -06:00
tangxifan 1e6955aaa4 rename arch directory to be clear for its usage 2020-07-04 19:13:28 -06:00