3 Commits

Author	SHA1	Message	Date
tangxifan	d36d1ebee2	[HDL] Temporarily disable WLR func in primitive HDL modeling	2021-09-20 17:07:51 -07:00
tangxifan	5c1c428ea5	[HDL] Updated cell library with the SRAM cell with Read Enable signal	2021-09-20 11:13:36 -07:00
tangxifan	019208ec0f	[Architecture] Reorganize the cell netlists and update architecture files accordingly	2020-09-25 11:55:28 -06:00