riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
4,011 Commits 70 Branches 8 Tags 105 MiB
Commit Graph

2 Commits

Author SHA1 Message Date
tangxifan ec184ef532 [Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF 2021-10-30 14:46:12 -07:00
Ganesh Gore 9ab57d1b2e Added fpga_flow script - Working Yosys 2019-08-09 16:49:05 -06:00