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OpenFPGA
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6670 Commits

Author SHA1 Message Date
tangxifan de6956530f [core] disable pnr sdc for tile-based fabric 2023-07-25 15:38:41 -07:00
tangxifan 6ecbbb3a94 [core] fixed a bug in fabric bitgen due to tile modules 2023-07-25 14:49:12 -07:00
tangxifan 95a32628ab [core] fixed the bug in arch bitgen due to the tile modules 2023-07-25 14:15:15 -07:00
dependabot[bot] 81147c3c3f
Bump yosys from `d5d2bf8` to `b04d0e0` 
Bumps [yosys](https://github.com/YosysHQ/yosys) from `d5d2bf8` to `b04d0e0`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](d5d2bf815a...b04d0e09e8)

---
updated-dependencies:
- dependency-name: yosys
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2023-07-25 06:53:46 +00:00
tangxifan 64698443c9 [core] fixed a bug on io location map for tile modules 2023-07-24 22:11:57 -07:00
tangxifan 2105abdbca [core] fixed a bug 2023-07-24 21:26:29 -07:00
tangxifan e7d714b94d [core] fixed a bug on the tile module port addition: some grid output was not pulled out 2023-07-24 21:21:25 -07:00
tangxifan b8d080b08e [core] fixed a bug where undriven cb ports are not connected to tile 2023-07-24 20:40:25 -07:00
tangxifan 3745897ff6 [core] fixed a few bugs 2023-07-24 16:10:29 -07:00
tangxifan 48b0ba8b78 [core] format 2023-07-24 15:00:26 -07:00
tangxifan 4294914987 [core] fixed compiler warnings 2023-07-24 14:59:43 -07:00
tangxifan 812473ef04 [core] fixed the bug on io location map for tiled top module 2023-07-24 14:50:39 -07:00
tangxifan da36b735c6 [core] syntax 2023-07-24 12:13:45 -07:00
chungshien 854649903d
Merge branch 'master' into openfpga-issue-1256 2023-07-24 11:41:32 -07:00
tangxifan f031148959 [core] syntax 2023-07-23 22:39:36 -07:00
tangxifan f551188d0f [core] developed tile directs to support tile modules 2023-07-23 21:45:45 -07:00
tangxifan 14666f3ae5 [core] sync 2023-07-23 20:45:59 -07:00
tangxifan 7783229d90 Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into xt_fabric_tile 2023-07-23 20:44:50 -07:00
tangxifan b72ec03067
Merge pull request #1260 from lnis-uofu/dependabot/submodules/yosys-d5d2bf8 
Bump yosys from `83c9261` to `d5d2bf8`
 2023-07-23 19:54:55 -07:00
tangxifan a25b61b382
Merge pull request #1258 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2023-07-23 19:54:37 -07:00
tangxifan 0b3b7b5472 [core] hotfix 2023-07-23 13:39:06 -07:00
tangxifan 1ee7448070 [core] supporting tile annotation (for global port) in tile modules 2023-07-23 13:38:16 -07:00
tangxifan 399259ea1d [core] adding prog clock arch support for tile modules 2023-07-23 13:11:13 -07:00
tangxifan 0f3f4b0d81 [core] now tile module use unique port name (for heterogeneous blocks) 2023-07-22 23:55:54 -07:00
tangxifan 003d9515ff [core] developing tile-based top module builder 2023-07-22 17:13:30 -07:00
tangxifan 93c5a68592 [core] developing top-level nets for tiles 2023-07-21 23:21:53 -07:00
Chung Shien Chai 6c03819c5f 100% limited new flow for flatten bl/wl protocol 2023-07-21 03:14:26 -07:00
dependabot[bot] 9afab9841b
Bump yosys from `83c9261` to `d5d2bf8` 
Bumps [yosys](https://github.com/YosysHQ/yosys) from `83c9261` to `d5d2bf8`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](83c9261d6c...d5d2bf815a)

---
updated-dependencies:
- dependency-name: yosys
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2023-07-21 06:16:37 +00:00
tangxifan fcf308fcd6 [core] developing inter-tile connections for top module 2023-07-20 23:00:35 -07:00
Chung Shien Chai 39934f9d16 Address issue 1256 2023-07-20 22:34:18 -07:00
tangxifan b70f7fb1b6 [core] now option conflicts in command 'build_fabric' can error out 2023-07-20 21:22:07 -07:00
tangxifan 6b92299e39 [core] start working on the net build-up for tile instances under the top-level module 2023-07-20 17:38:13 -07:00
tangxifan 88c5d122ca [core] syntax 2023-07-20 17:12:10 -07:00
tangxifan db179ec4bb [core] split tile instance builder and the classic fine-grained builder 2023-07-20 17:07:07 -07:00
github-actions[bot] ae9190f051 Updated Patch Count 2023-07-21 00:03:31 +00:00
tangxifan ef214f4590 [core] code format 2023-07-20 17:00:29 -07:00
tangxifan 6458580e3e [core] move child instance builder to a separated source file as these codes are expanding in size 2023-07-20 16:59:39 -07:00
tangxifan bd265334b5 [core] added tile instances to top module builder 2023-07-19 23:26:55 -07:00
tangxifan a06b9a0f48 [core] now start to develop the tile instances under the top module 2023-07-19 22:22:07 -07:00
tangxifan a09c67bd9f
Merge pull request #1257 from lnis-uofu/dependabot/submodules/yosys-83c9261 
Bump yosys from `25d4b3a` to `83c9261`
 2023-07-19 19:43:09 -07:00
tangxifan 7607ad69b1
Merge pull request #1252 from chungshien/openfpga-issues-1248 
Issue 1248 - fix bug bintoi_charvec()
 2023-07-19 19:40:43 -07:00
tangxifan 2e69eebea0 [core] now tile module builder is working 2023-07-19 17:23:44 -07:00
tangxifan 0d03d7b483 [core] now fabric tile cache both grid and gsb coord for pb 2023-07-19 17:20:53 -07:00
tangxifan 778d03610c [core] debugging 2023-07-19 15:27:05 -07:00
tangxifan 001b3b3f8b [core] debugging 2023-07-19 14:38:07 -07:00
tangxifan d03fa92ddf [core] debugging 2023-07-19 12:49:35 -07:00
tangxifan 48e207d3e4 [core] debugging 2023-07-19 12:22:57 -07:00
tangxifan 82fe63297a [test] add a new test for top-left tile grouping 2023-07-19 11:22:36 -07:00
dependabot[bot] 1a864d33b6
Bump yosys from `25d4b3a` to `83c9261` 
Bumps [yosys](https://github.com/YosysHQ/yosys) from `25d4b3a` to `83c9261`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](25d4b3a5dc...83c9261d6c)

---
updated-dependencies:
- dependency-name: yosys
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2023-07-19 06:06:53 +00:00
tangxifan 6607bb7e48 [core] now fpga verilog supports tile modules 2023-07-18 22:35:22 -07:00